|
6 | 6 | */
|
7 | 7 |
|
8 | 8 | #include "fsl_flexspi_nor_boot.h"
|
9 |
| -#include "fsl_flexspi_nor_config.h" |
| 9 | +#include "boards/board.h" |
10 | 10 |
|
11 | 11 |
|
12 | 12 | __attribute__((section(".boot_hdr.ivt")))
|
@@ -35,88 +35,135 @@ const BOOT_DATA_T boot_data = {
|
35 | 35 | 0xFFFFFFFF /* empty - extra data word */
|
36 | 36 | };
|
37 | 37 |
|
| 38 | +// Config for W25Q32JV with QSPI routed. |
38 | 39 | __attribute__((section(".boot_hdr.conf")))
|
39 |
| -// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39 |
40 | 40 | const flexspi_nor_config_t qspiflash_config = {
|
| 41 | + .pageSize = 256u, |
| 42 | + .sectorSize = 4u * 1024u, |
| 43 | + .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, |
| 44 | + .blockSize = 0x00010000, |
| 45 | + .isUniformBlockSize = false, |
41 | 46 | .memConfig =
|
42 | 47 | {
|
43 | 48 | .tag = FLEXSPI_CFG_BLK_TAG,
|
44 | 49 | .version = FLEXSPI_CFG_BLK_VERSION,
|
45 | 50 | .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
46 |
| - .csHoldTime = 1u, |
47 |
| - .csSetupTime = 2u, |
48 |
| - // Enable DDR mode, Wordaddressable, Safe configuration, Differential clock |
| 51 | + .csHoldTime = 3u, |
| 52 | + .csSetupTime = 3u, |
| 53 | + |
| 54 | + .busyOffset = 0u, // Status bit 0 indicates busy. |
| 55 | + .busyBitPolarity = 0u, // Busy when the bit is 1. |
| 56 | + |
| 57 | + .deviceModeCfgEnable = 1u, |
| 58 | + .deviceModeType = kDeviceConfigCmdType_QuadEnable, |
| 59 | + .deviceModeSeq = { |
| 60 | + .seqId = 4u, |
| 61 | + .seqNum = 1u, |
| 62 | + }, |
| 63 | + .deviceModeArg = 0x02, // Bit pattern for setting Quad Enable. |
49 | 64 | .deviceType = kFlexSpiDeviceType_SerialNOR,
|
50 | 65 | .sflashPadType = kSerialFlash_4Pads,
|
51 |
| - .serialClkFreq = kFlexSpiSerialClk_60MHz, // 03 |
| 66 | + .serialClkFreq = kFlexSpiSerialClk_133MHz, |
52 | 67 | .sflashA1Size = FLASH_SIZE,
|
53 | 68 | .lookupTable =
|
54 | 69 | {
|
55 | 70 | // FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
|
56 |
| - // (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | |
57 |
| - // FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) |
58 |
| - // Read LUTs |
59 |
| - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), |
60 |
| - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), |
61 |
| - 0, |
62 |
| - 0, |
63 |
| - |
64 |
| - 0x24040405, |
65 |
| - 0, |
66 |
| - 0, |
67 |
| - 0, |
68 |
| - |
69 |
| - 0, |
70 |
| - 0, |
71 |
| - 0, |
72 |
| - 0, |
73 |
| - |
74 |
| - 0x00000406, |
75 |
| - 0, |
76 |
| - 0, |
77 |
| - 0, |
78 |
| - |
79 |
| - 0, |
80 |
| - 0, |
81 |
| - 0, |
82 |
| - 0, |
83 |
| - |
84 |
| - 0x08180420, |
85 |
| - 0, |
86 |
| - 0, |
87 |
| - 0, |
88 |
| - |
89 |
| - 0, |
90 |
| - 0, |
91 |
| - 0, |
92 |
| - 0, |
93 |
| - |
94 |
| - 0, |
95 |
| - 0, |
96 |
| - 0, |
97 |
| - 0, |
98 |
| - |
99 |
| - 0x081804D8, |
100 |
| - 0, |
101 |
| - 0, |
102 |
| - 0, |
103 |
| - |
104 |
| - 0x08180402, |
105 |
| - 0x00002004, |
106 |
| - 0, |
107 |
| - 0, |
108 |
| - |
109 |
| - 0, |
110 |
| - 0, |
111 |
| - 0, |
112 |
| - 0, |
113 |
| - |
114 |
| - 0x00000460, |
| 71 | + // The high 16 bits is command 1 and the low are command 0. |
| 72 | + // Within a command, the top 6 bits are the opcode, the next two are the number |
| 73 | + // of pads and then last byte is the operand. The operand's meaning changes |
| 74 | + // per opcode. |
| 75 | + |
| 76 | + // Indices with ROM should always have the same function because the ROM |
| 77 | + // bootloader uses it. |
| 78 | + |
| 79 | + // 0: ROM: Read LUTs |
| 80 | + // Quad version |
| 81 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB /* the command to send */, |
| 82 | + RADDR_SDR, FLEXSPI_4PAD, 24 /* bits to transmit */), |
| 83 | + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 6 /* 6 dummy cycles, 2 for M7-0 and 4 dummy */, |
| 84 | + READ_SDR, FLEXSPI_4PAD, 0x04), |
| 85 | + // Single fast read version, good for debugging. |
| 86 | + // FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x0B /* the command to send */, |
| 87 | + // RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), |
| 88 | + // FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_1PAD, 8 /* 8 dummy clocks */, |
| 89 | + // READ_SDR, FLEXSPI_1PAD, 0x04), |
| 90 | + TWO_EMPTY_STEPS, |
| 91 | + TWO_EMPTY_STEPS), |
| 92 | + |
| 93 | + // 1: ROM: Read status |
| 94 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05 /* the command to send */, |
| 95 | + READ_SDR, FLEXSPI_1PAD, 0x02), |
| 96 | + TWO_EMPTY_STEPS, |
| 97 | + TWO_EMPTY_STEPS, |
| 98 | + TWO_EMPTY_STEPS), |
| 99 | + |
| 100 | + // 2: Empty |
| 101 | + EMPTY_SEQUENCE, |
| 102 | + |
| 103 | + // 3: ROM: Write Enable |
| 104 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06 /* the command to send */, |
| 105 | + STOP, FLEXSPI_1PAD, 0x00), |
| 106 | + TWO_EMPTY_STEPS, |
| 107 | + TWO_EMPTY_STEPS, |
| 108 | + TWO_EMPTY_STEPS), |
| 109 | + |
| 110 | + // 4: Config: Write Status -2 |
| 111 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x31 /* the command to send */, |
| 112 | + WRITE_SDR, FLEXSPI_1PAD, 0x01 /* number of bytes to write */), |
| 113 | + TWO_EMPTY_STEPS, |
| 114 | + TWO_EMPTY_STEPS, |
| 115 | + TWO_EMPTY_STEPS), |
| 116 | + |
| 117 | + // 5: ROM: Erase Sector |
| 118 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20 /* the command to send */, |
| 119 | + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), |
| 120 | + TWO_EMPTY_STEPS, |
| 121 | + TWO_EMPTY_STEPS, |
| 122 | + TWO_EMPTY_STEPS), |
| 123 | + |
| 124 | + // 6: Empty |
| 125 | + EMPTY_SEQUENCE, |
| 126 | + |
| 127 | + // 7: Empty |
| 128 | + EMPTY_SEQUENCE, |
| 129 | + |
| 130 | + // 8: Block Erase |
| 131 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8 /* the command to send */, |
| 132 | + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), |
| 133 | + TWO_EMPTY_STEPS, |
| 134 | + TWO_EMPTY_STEPS, |
| 135 | + TWO_EMPTY_STEPS), |
| 136 | + |
| 137 | + // 9: ROM: Page program |
| 138 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02 /* the command to send */, |
| 139 | + RADDR_SDR, FLEXSPI_1PAD, 24 /* bits to transmit */), |
| 140 | + |
| 141 | + FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04 /* data out */, |
| 142 | + STOP, FLEXSPI_1PAD, 0), |
| 143 | + TWO_EMPTY_STEPS, |
| 144 | + TWO_EMPTY_STEPS), |
| 145 | + |
| 146 | + // 10: Empty |
| 147 | + EMPTY_SEQUENCE, |
| 148 | + |
| 149 | + // 11: ROM: Chip erase |
| 150 | + SEQUENCE(FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60 /* the command to send */, |
| 151 | + STOP, FLEXSPI_1PAD, 0), |
| 152 | + TWO_EMPTY_STEPS, |
| 153 | + TWO_EMPTY_STEPS, |
| 154 | + TWO_EMPTY_STEPS), |
| 155 | + |
| 156 | + // 12: Empty |
| 157 | + EMPTY_SEQUENCE, |
| 158 | + |
| 159 | + // 13: ROM: Read SFDP |
| 160 | + EMPTY_SEQUENCE, |
| 161 | + |
| 162 | + // 14: ROM: Restore no cmd |
| 163 | + EMPTY_SEQUENCE, |
| 164 | + |
| 165 | + // 15: ROM: Dummy |
| 166 | + EMPTY_SEQUENCE |
115 | 167 | },
|
116 | 168 | },
|
117 |
| - .pageSize = 256u, |
118 |
| - .sectorSize = 4u * 1024u, |
119 |
| - .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz, |
120 |
| - .blockSize = 0x00010000, |
121 |
| - .isUniformBlockSize = false, |
122 | 169 | };
|
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