rp2 I2SOut: support both order for BCLK and LRCLK pins#9097
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dhalbert merged 1 commit intoadafruit:mainfrom Mar 26, 2024
Merged
rp2 I2SOut: support both order for BCLK and LRCLK pins#9097dhalbert merged 1 commit intoadafruit:mainfrom
dhalbert merged 1 commit intoadafruit:mainfrom
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This looks good to me! Could you test it on hardware with both orders on a Pico or other board? If you have done so already, great. I just want to make sure there hasn't been a regression. |
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I tested it on my hardware only, so the LRCLK before BCLK case. |
dhalbert
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Thanks for the testing on your board. I tested on an Adafruit Feather RP2040 Prop-Maker, and it worked fine.
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I am working on CicruitPython support for a board with an I2S DAC. The bit clock (BCLK) and word clock (LRCLK) pins are in a different order than what is currently expected in I2SOut.c.
I followed the suggestion in #8680 by adding two I2S programs with swapped sideset values to be able to support either configurations.