This repo contains a set of configured example designs that demonstrate different features of the FPGA AI Suite. The FPGA AI Suite is a collection of tools for efficiently running AI inference on Altera FPGAs. The examples in this repo cover the different development boards, connectivity types, and FPGA families that the AI Suite supports.
Each example will walk you through a standard workflow to demonstrate how to use to the AI Suite to:
- Compile the AI Suite IP into an FPGA bitstream.
- Program an FPGA with the AI Suite IP bitstream.
- Prepare an AI model graph for inference.
- Run inference on an FPGA using a benchmark dataset.
You may obtain a copy of the FPGA AI Suite from the official downloads page.
Important
All examples have a hard limit of 10'000 inference requests. Please refer to the documentation on "--licensed/--unlicensed" IP generation for details about this limitation.
Full details on how to install the FPGA AI Suite, including all software and hardware requirements, are available in Chapter 4 of the Getting Started Guide. The individual READMEs for each example also contain any additional requirements and setup instructions that are particular to that example.
Hostless example designs demonstrate how to directly control the FPGA AI Suite IP over JTAG.
| Family | Development Board |
|---|---|
| Agilex 5 | Agilex 5E Modular Development Kit |
PCIe-attach example designs demonstrate how a host computer can use the FPGA AI Suite to offload AI workloads onto an FPGA via PCIe.
| Family | Development Board |
|---|---|
| Agilex 7 | Terasic DE10-Agilex Development Board |
| Agilex 7 | Agilex 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile) |
| Agilex 7 | Intel FPGA SmartNIC N6001-PL Platform (without an Ethernet controller) |