Updates on the Stingray devicetree #3047
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When the data offload is configured on the RX side the oneshot is enabled by default, if the user needs the offload to be bypassed the control register will be 0x3 instead of 0x1. bit 0- controls the bypass bit 1- controls the oneshot Signed-off-by: PopPaul2021 <[email protected]>
In the updated HDL project the CDC was moved from the DO to the DMA and the cache coherency was disabled in order to have the HP ports working at maximum frequency. Signed-off-by: PopPaul2021 <[email protected]>
PopPaul2021
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CiprianRegus,
amiclaus,
btogorean,
buha,
chegbeli,
danmois,
dbogdan,
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mhennerich,
nunojsa and
rbolboac
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nunojsa
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Dec 15, 2025
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It seems there various style complains. Please address them...
Also follow guidelines for commit messages in the kernel. Example, run git log --oneline arch/arm64/boot/dts/xilinx/ and see the style used the most (In our tree you won't likely see an unified style but I'm trying to change that :)). Same goes for the driver patch
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PR Description
In the updated HDL project the CDC was moved from the DO to the DMA and the cache coherency was disabled in order to have the HP ports working at maximum frequency.
When the data offload is configured on the RX side the oneshot is enabled by default, if the user needs the offload to be bypassed the control register will be 0x3 instead of 0x1.
bit 0- controls the bypass
bit 1- controls the oneshot
PR Type
PR Checklist