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[backport] gpio: core: Decouple open drain/source flag with active low/high #89
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…w/high Note [Alexandru Ardelean]: the SidekiqZ2 reset pin is an open drain, however it doesn't behave like one when the `ad9361_reset()` code runs. Because the GPIO_OPEN_DRAIN OF property has the GPIO_ACTIVE_LOW flag, the value is inverted. So, when doing `gpiod_set_value(0)` the final open-drain code is `_gpio_set_open_drain_value(1)`, which is not what we want. [ upstream commit 4c0facd ("gpio: core: Decouple open drain/source flag with active low/high") ] Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single Ended and active HIGH. The active HIGH/LOW is used in the interface for setting the pin state to HIGH or LOW when enabling/disabling the interface. In Open Drain interface, pin is set to HIGH by putting pin in high impedance and LOW by driving to the LOW. In Open Source interface, pin is set to HIGH by driving pin to HIGH and set to LOW by putting pin in high impedance. With above, the Open Drain/Source is unrelated to the active LOW/HIGH in interface. There is interface where the enable/disable of interface is ether active LOW or HIGH but it is Open Drain type. Hence decouple the Open Drain with Single Ended + Active LOW and Open Source with Single Ended + Active HIGH. Adding different flag for the Open Drain/Open Source which is valid only when Single ended flag is enabled. Signed-off-by: Laxman Dewangan <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
dbogdan
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May 9, 2018
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Hm, interesting that they are breaking the ABI. |
lclausen-adi
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May 9, 2018
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Chagelog v1 => v2:
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@lclausen-adi yeah it is interesting ; i was a bit puzzled why open-drain wasn't behaving in the kernel as an open drain i also did a quick grep in our DTs to check that we don't have any other open-drains or open-sources ; |
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Will merge this later today if no objections |
mhennerich
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May 9, 2018
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…ze (analogdevicesinc#89) Added a check for AES block mode and param size before the value is send to secure world. Reject request if block mode or param size is incorrect. Signed-off-by: Teh Wen Ping <[email protected]>
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…ze (#89) Added a check for AES block mode and param size before the value is send to secure world. Reject request if block mode or param size is incorrect. Signed-off-by: Teh Wen Ping <[email protected]>
podgori
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…ze (#89) Added a check for AES block mode and param size before the value is send to secure world. Reject request if block mode or param size is incorrect. Signed-off-by: Teh Wen Ping <[email protected]>
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Note [Alexandru Ardelean]: the SidekiqZ2 reset pin is an open drain, however it doesn't behave like one when the
ad9361_reset()code runs. Because the GPIO_OPEN_DRAIN OF property has the GPIO_ACTIVE_LOW flag, the value is inverted. So, when doinggpiod_set_value(0)the final open-drain code is_gpio_set_open_drain_value(1), which is not what we want.[ upstream commit 4c0facd ("gpio: core: Decouple open drain/source
flag with active low/high") ]
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH/LOW is used in the interface for setting the pin
state to HIGH or LOW when enabling/disabling the interface.
In Open Drain interface, pin is set to HIGH by putting pin in
high impedance and LOW by driving to the LOW.
In Open Source interface, pin is set to HIGH by driving pin to
HIGH and set to LOW by putting pin in high impedance.
With above, the Open Drain/Source is unrelated to the active LOW/HIGH
in interface. There is interface where the enable/disable of interface
is ether active LOW or HIGH but it is Open Drain type.
Hence decouple the Open Drain with Single Ended + Active LOW and
Open Source with Single Ended + Active HIGH.
Adding different flag for the Open Drain/Open Source which is valid
only when Single ended flag is enabled.
Signed-off-by: Laxman Dewangan [email protected]
Signed-off-by: Linus Walleij [email protected]