Please model non-taken branches as 1*p06 on hsw/skl

[amonakov]

At the moment uica removes p0 as a possible execution port on hsw/skl for a branch early on:

uiCA/convertXML.py

Lines 95 to 96 in 9cbbe93

	if (archNode.attrib['name'] not in ['ICL', 'TGL', 'RKL', 'ADL-P']) and (XMLInstr.attrib['category'] == 'COND_BR') and (ports == '1*p06'):
	ports = '1*p6' # taken branches can only use port 6

I'd like to suggest that this should be done only for the branch that terminates the input basic block. If the user provided a snippet that contains extra branches in the middle, like I did in issue #14 earlier, they are assumed to be never taken, and hence modeling them as occupying either port 0 or port 6 would be more accurate.

edit: to be clear, I understand that with extra branches the input snippet is not a basic block (potentially an "extended basic block" in compiler developer speak, if jumping into it after the first instruction is impossible)