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problem in parsing system verilog files

Status: Open.

#692 In chipfoundry/openlane2;

· tupur25 opened on Oct 31, 2025

klayout having unexpected behavior in nix shell

Status: Open.

#689 In chipfoundry/openlane2;

· link422 opened on Jun 16, 2025

Incorrect frequency calculation in clock period example

Status: Open.

#687 In chipfoundry/openlane2;

· vamshiKrishnaReddy20 opened on May 22, 2025

PDN Generation Error

Status: Open.

#684 In chipfoundry/openlane2;

· nishit0072e opened on Mar 29, 2025

PRIMARY_GDSII_STREAMOUT_TOOL behavior/doc

Status: Open.

#683 In chipfoundry/openlane2;

· smunaut opened on Mar 6, 2025

Yosys fails fatally on empty designs

Status: Open.

#681 In chipfoundry/openlane2;

· smunaut opened on Mar 5, 2025

Add support for Verilator configuration (<code>.vlt</code>) files

Status: Open.

#680 In chipfoundry/openlane2;

· soronpo opened on Feb 27, 2025

GHDL not available on aarch64 platforms

⛔️ blockedThis issue or PR is pending an issue with an underlying utilityThis issue or PR is pending an issue with an underlying utility

🐞 bugSomething isn't workingSomething isn't working

Status: Open.

#674 In chipfoundry/openlane2;

· fred-corp opened on Feb 19, 2025

Failed to get Nix info: [Errno 2] No such file or directory: 'nix'

🐞 bugSomething isn't workingSomething isn't working

Status: Open.

#671 In chipfoundry/openlane2;

· mguthaus opened on Feb 18, 2025

Optimize corners in reszier steps

Status: Open.

#668 In chipfoundry/openlane2;

· kareefardi opened on Feb 17, 2025

Signoff Regression

✨ enhancementNew feature or requestNew feature or request

Status: Open.

#659 In chipfoundry/openlane2;

· donn opened on Feb 11, 2025

Support custom RC values by corner

✨ enhancementNew feature or requestNew feature or request

Status: Open.

#657 In chipfoundry/openlane2;

· donn opened on Feb 9, 2025