docs: Describe AXI Streaming Boot Sequence#546
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docs: Describe AXI Streaming Boot Sequence#546tmichalak wants to merge 1 commit intochipsalliance:mainfrom
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bluegate010
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Sep 3, 2025
doc/Caliptra.md
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| # AXI Streaming Boot Sequence | ||
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| The I3C core alternatively allows streaming data or firmware by MCU over the AXI bus of the I3C module which is repurposed as a streaming boot interface while disabling I3C usage. | ||
| The Caliptra MCU RISC-V core is responsible for driving the data copied from an external memory (e.g. QSPI interface) to the streaming boot FIFOs. |
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| The Caliptra MCU RISC-V core is responsible for driving the data copied from an external memory (e.g. QSPI interface) to the streaming boot FIFOs. | |
| The Caliptra MCU RISC-V core is responsible for driving the data copied from an external memory interface (e.g. QSPI) to the streaming boot FIFOs. |
doc/Caliptra.md
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| 5. Write to the `INDIRECT_FIFO_CTRL` register to set the streaming boot image size | ||
| 6. Push the image/data to the streaming boot interface FIFOs: | ||
| 1. Read the `INDIRECT_FIFO_STATUS` register to determine remaining space in the indirect FIFO | ||
| 2. If the indirect FIFO is not full, write a chunk of data to the `TX_DATA_PORT` register |
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What should MCU ROM do if the FIFO is full?
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Added a bullet regarding such path.
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Adds description of the AXI Streaming Boot Flow. Complementary to chipsalliance/caliptra-ss#658