[RTL] Add RDC gated clocks and resets (#279)

clayton8 · web-flow · commit 0b6a805e8983 · 2025-04-13T22:23:40.000-06:00
* Add RDC controls to mci_boot_seqr

* [RTL] Connect RDC reset and Clocks to IPs

RDC gated clockes have been connected to MCI and MCU due to reset
domain crossings

Connect I3C, LCC, MCI, and FC to new synchronized reset generated
by MCI. This reset is alsigned with RDC gated clocks. It isn't required
for I3C, LCC, and FC since they don't have RDC issues due to one clock domain.
But this is a cleaner design to have all these IPs come out of reset at the same
time.

Note: RDC architecture mirrors Caliptra RDC implementation.

* MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-rdc-changes-2' with updated timestamp and hash after successful run
diff --git a/.github/workflow_metadata/pr_hash b/.github/workflow_metadata/pr_hash
@@ -1 +1 @@
-cc6f0ba0d9d73005640a2a8b9170976922320a504cecf11e087acd9a41d475f1edae2e326d1363eca081ecdb3afdfc4a
+8fcecd8df0e636fa5009731edf28dac6c9ffc6071041ffe139fd6462a024f6bd05fdf35aed46eaff8c0ac28bb8359b16
diff --git a/.github/workflow_metadata/pr_timestamp b/.github/workflow_metadata/pr_timestamp
@@ -1 +1 @@
-1744455972
+1744604477
diff --git a/src/integration/rtl/caliptra_ss_top.sv b/src/integration/rtl/caliptra_ss_top.sv
@@ -290,6 +290,10 @@ module caliptra_ss_top
     logic [11:0]                wb_csr_dest;
     logic [31:0]                wb_csr_data;
 
+    logic cptra_ss_rst_b_o;
+
+    logic mcu_clk_cg;
+
     logic        mcu_dmi_core_enable;
     logic        mcu_dmi_uncore_enable;
     logic        mcu_dmi_uncore_en;
@@ -569,12 +573,12 @@ module caliptra_ss_top
 
     mci_mcu_sram_if cptra_ss_mcu_rom_mbox0_sram_req_if (
         .clk(cptra_ss_clk_i),
-        .rst_b(cptra_ss_rst_b_i)
+        .rst_b(cptra_ss_rst_b_o)
     );
     
     mci_mcu_sram_if cptra_ss_mcu_rom_mbox1_sram_req_if (
         .clk(cptra_ss_clk_i),
-        .rst_b(cptra_ss_rst_b_i)
+        .rst_b(cptra_ss_rst_b_o)
     );
 
 
@@ -778,7 +782,7 @@ module caliptra_ss_top
     mcu_top rvtop_wrapper (
         .rst_l                  ( mcu_rst_b ),
         .dbg_rst_l              ( cptra_ss_pwrgood_i ), //FIXME same as caliptra?
-        .clk                    ( cptra_ss_clk_i ),
+        .clk                    ( mcu_clk_cg ),
         .rst_vec                ( reset_vector[31:1]),
         .nmi_int                ( mci_mcu_nmi_int),
         .nmi_vec                ( mci_mcu_nmi_vector[31:1]),
@@ -1075,7 +1079,7 @@ module caliptra_ss_top
         .AxiIdWidth  (`AXI_ID_WIDTH  )
     ) i3c (
         .clk_i (cptra_ss_clk_i),
-        .rst_ni(cptra_ss_rst_b_i),
+        .rst_ni(cptra_ss_rst_b_o),
 
         .arvalid_i  (cptra_ss_i3c_s_axi_if.arvalid),
         .arready_o  (cptra_ss_i3c_s_axi_if.arready),
@@ -1141,7 +1145,7 @@ module caliptra_ss_top
       .IW(8)
     ) mcu_rom_i (
       .clk(cptra_ss_clk_i),
-      .rst_n(cptra_ss_rst_b_i),
+      .rst_n(cptra_ss_rst_b_o),
 
       .s_axi_r_if(cptra_ss_mcu_rom_s_axi_if.r_sub),
       .s_axi_w_if(cptra_ss_mcu_rom_s_axi_if.w_sub),
@@ -1172,8 +1176,13 @@ module caliptra_ss_top
     ) mci_top_i (
 
         .clk(cptra_ss_clk_i),
+        .mcu_clk_cg(mcu_clk_cg),
+        .cptra_ss_rdc_clk_cg(), // Unused since no IPs on warm reset. MCU has different clock and Cptra has its own RDC.
+
+
         .mci_rst_b(cptra_ss_rst_b_i),
         .mci_pwrgood(cptra_ss_pwrgood_i),
+        .cptra_ss_rst_b_o(cptra_ss_rst_b_o),
         
         // DFT
         .scan_mode     (cptra_ss_cptra_core_scan_mode_i),
@@ -1316,7 +1325,7 @@ module caliptra_ss_top
 
     lc_ctrl u_lc_ctrl (
             .clk_i(cptra_ss_clk_i),
-            .rst_ni(cptra_ss_rst_b_i),
+            .rst_ni(cptra_ss_rst_b_o),
             .Allow_RMA_or_SCRAP_on_PPD(cptra_ss_lc_Allow_RMA_or_SCRAP_on_PPD_i),
             .axi_wr_req(cptra_ss_lc_axi_wr_req_i),
             .axi_wr_rsp(cptra_ss_lc_axi_wr_rsp_o),
@@ -1384,7 +1393,7 @@ module caliptra_ss_top
         .MemInitFile ("otp-img.2048.vmem")
     ) u_otp_ctrl (
         .clk_i                      (cptra_ss_clk_i),
-        .rst_ni                     (cptra_ss_rst_b_i),
+        .rst_ni                     (cptra_ss_rst_b_o),
         .FIPS_ZEROIZATION_CMD_i     (FIPS_ZEROIZATION_CMD),
 
         .cptra_ss_strap_mcu_lsu_axi_user_i  (cptra_ss_strap_mcu_lsu_axi_user_i),
@@ -1436,9 +1445,4 @@ module caliptra_ss_top
         .cio_test_en_o              ()    //TODO: Needs to be checked
 	); 
 
-    // assign fuse_ctrl_rdy = 1;
-    // De-assert cptra_rst_b only after fuse_ctrl has initialized
-    logic cptra_rst_b; //fixme resets
-    assign cptra_rst_b = cptra_ss_rst_b_i;//fuse_ctrl_rdy ? cptra_soc_bfm_rst_b : 1'b0;
-
 endmodule
diff --git a/src/mci/rtl/mci_boot_seqr.sv b/src/mci/rtl/mci_boot_seqr.sv
@@ -23,11 +23,17 @@ import mci_pkg::*;
 (
     input logic clk,
     input logic mci_rst_b,
+    input logic mci_pwrgood,
+
+    // Clock Controls
+    output logic rdc_clk_dis,
+    output logic fw_update_rdc_clk_dis,
 
     // DFT
     input scan_mode,
 
     // Reset controls
+    output logic cptra_ss_rst_b_o,
     output logic mcu_rst_b,
     output logic cptra_rst_b,
 
@@ -62,20 +68,27 @@ import mci_pkg::*;
 mci_boot_fsm_state_e boot_fsm_nxt;
 mci_boot_fsm_state_e boot_fsm_prev;
 
-logic lc_done_sync;
 logic lc_init_nxt;
 
-logic fc_opt_done_sync;
 logic fc_opt_init_nxt;
 
 logic mci_boot_seq_brkpoint_sync;
+logic mcu_cpu_halt_ack_i_sync;
+logic mcu_cpu_halt_status_i_sync;
 
 logic mcu_no_rom_config_sync;
 
 logic mcu_rst_b_ff  ;
 logic cptra_rst_b_ff;
+logic cptra_ss_rst_b_o_ff;
 logic mcu_rst_b_nxt;
 logic cptra_rst_b_nxt;
+logic cptra_ss_rst_b_o_nxt;
+
+logic mci_rst_window;
+logic mci_rst_window_sync;
+logic fw_update_rst_window;
+logic warm_reset;
 
 logic mcu_reset_once_nxt;
 
@@ -88,97 +101,134 @@ logic min_mcu_rst_count_elapsed_nxt;
 /////////////////////////////////////////////////
 // DFT                                 
 /////////////////////////////////////////////////
-assign mcu_rst_b   = scan_mode ? mcu_rst_b   :  mcu_rst_b_ff;
-assign cptra_rst_b = scan_mode ? cptra_rst_b :  cptra_rst_b_ff;
+assign cptra_ss_rst_b_o   = scan_mode ? mci_rst_b           :  cptra_ss_rst_b_o_ff;
+assign mcu_rst_b          = scan_mode ? mci_rst_b           :  mcu_rst_b_ff;
+assign cptra_rst_b        = scan_mode ? mci_rst_b           :  cptra_rst_b_ff;
+
+/////////////////////////////////////////////////
+// Reset Window                        
+/////////////////////////////////////////////////
+
+//uC reset generation
+always_ff @(posedge clk or negedge mci_rst_b) begin
+    if (~mci_rst_b) begin
+        mci_rst_window <= '1;
+    end
+    else begin
+        mci_rst_window <= 0;
+    end
+end
+
+caliptra_2ff_sync #(.WIDTH(1), .RST_VAL('d1)) i_rst_window_sync (.clk(clk), .rst_b(mci_pwrgood), .din(mci_rst_window), .       dout(mci_rst_window_sync));
+
+//clock gate all flops on warm reset to prevent RDC metastability issues
+always_comb rdc_clk_dis = mci_rst_window_sync;
+
+
+assign warm_reset = mci_rst_window_sync;
+
+assign fw_update_rst_window = (boot_fsm_nxt == BOOT_RST_MCU) || (boot_fsm == BOOT_RST_MCU); 
+
+//clock gate all flops on MCU FW update
+assign fw_update_rdc_clk_dis = fw_update_rst_window; 
 
 /////////////////////////////////////////////////
 // Sync signals into local clock domain
 /////////////////////////////////////////////////
 caliptra_prim_flop_2sync #(
   .Width(1)
-) u_prim_flop_2sync_lc_done (
+) u_prim_flop_2sync_mci_boot_seq_brkpoint (
   .clk_i(clk),
-  .rst_ni(mci_rst_b),
-  .d_i(lc_done),
-  .q_o(lc_done_sync));
+  .rst_ni(mci_pwrgood),
+  .d_i(mci_boot_seq_brkpoint),
+  .q_o(mci_boot_seq_brkpoint_sync));
 
 caliptra_prim_flop_2sync #(
   .Width(1)
-) u_prim_flop_2sync_fc_opt_done (
+) u_prim_flop_2sync_mcu_no_rom_config (
   .clk_i(clk),
-  .rst_ni(mci_rst_b),
-  .d_i(fc_opt_done),
-  .q_o(fc_opt_done_sync));
+  .rst_ni(mci_pwrgood),
+  .d_i(mcu_no_rom_config),
+  .q_o(mcu_no_rom_config_sync));
+
 
 caliptra_prim_flop_2sync #(
   .Width(1)
-) u_prim_flop_2sync_mci_boot_seq_brkpoint (
+) u_prim_flop_2sync_mcu_cpu_halt_ack_i (
   .clk_i(clk),
-  .rst_ni(mci_rst_b),
-  .d_i(mci_boot_seq_brkpoint),
-  .q_o(mci_boot_seq_brkpoint_sync));
+  .rst_ni(mci_pwrgood),
+  .d_i(mcu_cpu_halt_ack_i),
+  .q_o(mcu_cpu_halt_ack_i_sync));
 
 caliptra_prim_flop_2sync #(
   .Width(1)
-) u_prim_flop_2sync_mcu_no_rom_config (
+) u_prim_flop_2sync_mcu_cpu_halt_status_i (
   .clk_i(clk),
-  .rst_ni(mci_rst_b),
-  .d_i(mcu_no_rom_config),
-  .q_o(mcu_no_rom_config_sync));
+  .rst_ni(mci_pwrgood),
+  .d_i(mcu_cpu_halt_status_i),
+  .q_o(mcu_cpu_halt_status_i_sync));
+
 
 /////////////////////////////////////////////////
 // Boot FSM
 /////////////////////////////////////////////////
-always_ff @(posedge clk or negedge mci_rst_b) begin
-    if(!mci_rst_b) begin
+always_ff @(posedge clk or negedge mci_pwrgood) begin
+    if(!mci_pwrgood) begin
         boot_fsm                    <= BOOT_IDLE;
         boot_fsm_prev               <= BOOT_IDLE;
         fc_opt_init                 <= '0;
         lc_init                     <= '0;
+        cptra_ss_rst_b_o_ff         <= '0;
         mcu_rst_b_ff                <= '0;
         cptra_rst_b_ff              <= '0;
         mcu_reset_once              <= '0;
         min_mcu_rst_count_elapsed   <= '0;
         min_mcu_rst_count           <= '0;
     end
     else begin
-        boot_fsm        <= boot_fsm_nxt;
-        boot_fsm_prev   <= (boot_fsm != boot_fsm_nxt) ? boot_fsm : boot_fsm_prev; // Capture where FSM came from
-        fc_opt_init     <= fc_opt_init_nxt;
-        lc_init         <= lc_init_nxt;
-        mcu_rst_b_ff    <= mcu_rst_b_nxt;
-        cptra_rst_b_ff  <= cptra_rst_b_nxt;
-        mcu_reset_once  <= mcu_reset_once_nxt;
-        min_mcu_rst_count_elapsed <= min_mcu_rst_count_elapsed_nxt;
-        min_mcu_rst_count <= min_mcu_rst_count_nxt;       
+        boot_fsm                    <= warm_reset ? BOOT_IDLE : boot_fsm_nxt;
+        boot_fsm_prev               <= (boot_fsm != boot_fsm_nxt) ? boot_fsm : boot_fsm_prev; // Capture where FSM came from
+        fc_opt_init                 <= fc_opt_init_nxt;
+        lc_init                     <= lc_init_nxt;
+        cptra_ss_rst_b_o_ff         <= cptra_ss_rst_b_o_nxt;
+        mcu_rst_b_ff                <= mcu_rst_b_nxt;
+        cptra_rst_b_ff              <= cptra_rst_b_nxt;
+        mcu_reset_once              <= mcu_reset_once_nxt;
+        min_mcu_rst_count_elapsed   <= min_mcu_rst_count_elapsed_nxt;
+        min_mcu_rst_count           <= min_mcu_rst_count_nxt;       
     end
 end
 
 
 always_comb begin
-    boot_fsm_nxt    = boot_fsm;
-    fc_opt_init_nxt = fc_opt_init;
-    lc_init_nxt     = lc_init;
-    mcu_rst_b_nxt   = mcu_rst_b_ff;
-    cptra_rst_b_nxt = cptra_rst_b_ff;
-    mcu_reset_once_nxt  = mcu_reset_once;
-    mcu_cpu_halt_req_nxt = 1'b0;
+    boot_fsm_nxt            = boot_fsm;
+    fc_opt_init_nxt         = fc_opt_init;
+    lc_init_nxt             = lc_init;
+    cptra_ss_rst_b_o_nxt    = cptra_ss_rst_b_o_ff;
+    mcu_rst_b_nxt           = mcu_rst_b_ff;
+    cptra_rst_b_nxt         = cptra_rst_b_ff;
+    mcu_reset_once_nxt      = mcu_reset_once;
+    mcu_cpu_halt_req_nxt    = 1'b0;
     unique case(boot_fsm)
         BOOT_IDLE: begin
             // Can only transition into IDLE on MCI reset
             // If this changes we need to add init signal values
             // for FC, LCC, MCU, CPTRA
-            boot_fsm_nxt = BOOT_OTP_FC; 
+            boot_fsm_nxt            = BOOT_OTP_FC; 
+            cptra_ss_rst_b_o_nxt    = 1'b0;
+            mcu_rst_b_nxt           = 1'b0;
+            cptra_rst_b_nxt         = 1'b0;
         end
         BOOT_OTP_FC: begin
+            cptra_ss_rst_b_o_nxt    = 1'b1;
             fc_opt_init_nxt = 1'b1;
-            if (fc_opt_done_sync) begin
+            if (fc_opt_done) begin
                 boot_fsm_nxt = BOOT_LCC; 
             end
         end
         BOOT_LCC: begin
             lc_init_nxt = 1'b1;
-            if(lc_done_sync) begin
+            if(lc_done) begin
                 boot_fsm_nxt = BOOT_BREAKPOINT_CHECK;
             end
         end
@@ -227,13 +277,13 @@ always_comb begin
             end
         end
         BOOT_HALT_MCU: begin
-            if(mcu_cpu_halt_ack_i) begin
+            if(mcu_cpu_halt_ack_i_sync) begin
                 boot_fsm_nxt        = BOOT_WAIT_MCU_HALTED;
             end
             mcu_cpu_halt_req_nxt = 1'b1;
         end
         BOOT_WAIT_MCU_HALTED: begin
-            if (mcu_cpu_halt_status_i) begin
+            if (mcu_cpu_halt_status_i_sync) begin
                 boot_fsm_nxt        = BOOT_RST_MCU;
             end
         end
@@ -254,8 +304,8 @@ always_comb begin
     endcase
 end
 
-always_ff@(posedge clk or negedge mci_rst_b) begin
-    if (!mci_rst_b) begin
+always_ff@(posedge clk or negedge mci_pwrgood) begin
+    if (!mci_pwrgood) begin
         mcu_cpu_halt_req_o <= 1'b0;
     end
     else begin
diff --git a/src/mci/rtl/mci_reg_top.sv b/src/mci/rtl/mci_reg_top.sv
@@ -553,7 +553,6 @@ always_comb mcu_sram_dmi_uncore_wdata = mcu_dmi_uncore_wdata;
 
 always_comb mci_reg_hwif_in.intr_block_rf.error0_internal_intr_r.error_mcu_sram_dmi_axi_collision_sts.hwset           = mcu_sram_dmi_axi_collision_error; // Set by any protocol error violation (mirrors the bits in CPTRA_HW_ERROR_NON_FATAL)
                                               
-// FIXME RDC clock?
 always_ff @(posedge clk or negedge mci_pwrgood) begin
     if (~mci_pwrgood) begin
       mcu_dmi_uncore_rdata <= '0;
@@ -821,7 +820,7 @@ assign mcu_nmi_vector = mci_reg_hwif_out.MCU_NMI_VECTOR.vec;
 // Write-enables for HW_ERROR_FATAL and HW_ERROR_NON_FATAL
 // Also calculate whether or not an unmasked event is being set, so we can
 // trigger the SOC interrupt signal
-always_comb mci_reg_hwif_in.HW_ERROR_FATAL.mcu_sram_ecc_unc.we  = mcu_sram_double_ecc_error; // FIXME do we need to add a reset window disable like in caliptra?
+always_comb mci_reg_hwif_in.HW_ERROR_FATAL.mcu_sram_ecc_unc.we  = mcu_sram_double_ecc_error;
 always_comb mci_reg_hwif_in.HW_ERROR_FATAL.nmi_pin     .we      = nmi_intr;
 always_comb mci_reg_hwif_in.HW_ERROR_FATAL.mcu_sram_dmi_axi_collision.we  = mcu_sram_dmi_axi_collision_error;
 // Using we+next instead of hwset allows us to encode the reserved fields in some fashion
@@ -1268,7 +1267,7 @@ assign mci_reg_hwif_in.intr_block_rf.notif0_internal_intr_r.notif_mcu_sram_ecc_c
 mci_reg i_mci_reg (
 
         .clk  (clk),
-        .rst  ('0), // FIXME why is this tied off in soc_ifc?
+        .rst  ('0), 
 
         .s_cpuif_req            (cif_resp_if.dv),
         .s_cpuif_req_is_wr      (cif_resp_if.req_data.write),
diff --git a/src/mci/rtl/mci_top.sv b/src/mci/rtl/mci_top.sv

Original file line number	Diff line number	Diff line change
`@@ -1 +1 @@`
`1`		`-cc6f0ba0d9d73005640a2a8b9170976922320a504cecf11e087acd9a41d475f1edae2e326d1363eca081ecdb3afdfc4a`
	`1`	`+8fcecd8df0e636fa5009731edf28dac6c9ffc6071041ffe139fd6462a024f6bd05fdf35aed46eaff8c0ac28bb8359b16`