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clayton8
commented
Apr 14, 2025
clayton8
commented
- Implement RDC architecture at Caliptra SS level which mirrors Caliptra RDC implementation.
- Connect I3C, LCC, and FC to new reset from MCI to ensure these all these IPs come out of reset at the same time.
RDC gated clockes have been connected to MCI and MCU due to reset domain crossings Connect I3C, LCC, MCI, and FC to new synchronized reset generated by MCI. This reset is alsigned with RDC gated clocks. It isn't required for I3C, LCC, and FC since they don't have RDC issues due to one clock domain. But this is a cleaner design to have all these IPs come out of reset at the same time. Note: RDC architecture mirrors Caliptra RDC implementation.
…ted timestamp and hash after successful run
bharatpillilli
approved these changes
Apr 14, 2025
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