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[RTL][VAL] MCU TB Trace Testing + MCI interrupt fixes + MCI AXI miss response change (#294)
* Add trace buffer val and fix mcu debug stress test Debug stress test uses functional unlocking instead of HW forces. Trace buffer monitor added to SOC BFM with assertions. All AXI trace buffer tests have been added with a few trace buffer RTL fixes. * [RTL] Error and intr connections to MCI and expose MCU halt status MCU halt status should be used by SOC for warm reset to avoid RDC issues. fc_intr_otp_error connected to MCI's AGG fatal/non-fatal infra. Connect intr_otp_operation_done to MCI instead of directly do MCU to give a more uniform interrupt structure for MCU. * [RTL] Block trace buffer WR if debug locked * Fix trace buffer no debug mode test * Fix table formatting in documentation * Trace buffer spec clarification * Fix lint issues in MCI * Remove unused DMI logic in MCI * HW spec updates Simplify MCI DMI Memory Map access table to show Debug intent == Manufacture mode access. Move MCI DMI Memory Map lower below the definitions used by the memory map table. Remove stal MCI DEBUG AXI USER documentation. We no longer have the concept as a Debug AXI user. * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-trace-buff-test' with updated timestamp and hash after successful run
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‎.github/workflow_metadata/pr_hash‎

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‎.github/workflow_metadata/pr_timestamp‎

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‎docs/CaliptraSSHardwareSpecification.md‎

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‎docs/CaliptraSSIntegrationSpecification.md‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,7 @@ File at path includes parameters and defines for Caliptra Subystem `src/integrat
357357
| External | output | 1 | `ready_for_fuses` | Ready for fuses output |
358358
| External | output | 1 | `ready_for_mb_processing` | Ready for mailbox processing output |
359359
| External | output | 1 | `mailbox_data_avail` | Mailbox data available output |
360+
| External | output | 1 | `cptra_ss_cpu_halt_status_o` | MCU Halt status |
360361

361362
## Integration Requirements
362363

@@ -1072,13 +1073,13 @@ If there is an issue within MCI whether it be the Boot Sequencer or another comp
10721073

10731074
- Top Level Memory Map
10741075

1075-
| Internal Block | Address Offset (from base address) |
1076-
| :---- | :---- |
1077-
| CSRs | 0x0 |
1078-
| MCU Trace Buffer | 0x10000 |
1079-
| Mailbox 0 | 0x400000|
1080-
| Mailbox 1 | 0x800000|
1081-
| MCU SRAM | 0xC00000 |
1076+
| Internal Block | Address Offset (from base address) | End Address|
1077+
| :---- | :---- | :---- |
1078+
| CSRs | 0x0 | 0x1FFF |
1079+
| MCU Trace Buffer | 0x10000 | 0x1001F |
1080+
| Mailbox 0 | 0x400000| 0x7FFFFF |
1081+
| Mailbox 1 | 0x800000| 0xBFFFFF |
1082+
| MCU SRAM | 0xC00000 | MCU SRAM BASE + MCU_SRAM_SIZE |
10821083

10831084
- MCU SRAM Memory Map
10841085

@@ -1123,7 +1124,7 @@ The two regions have different access protection. The size of the regions is dyn
11231124

11241125
To calculate the base address alignment use the following calculation:
11251126

1126-
bits = $clog2(MCU_SRAM_OFFSET + ((MCU\_SRAM\_SIZE\_KB * 1024) - 1))
1127+
bits = $clog2(MCU_SRAM_OFFSET + ((MCU_SRAM_SIZE_KB * 1024) - 1))
11271128

11281129
MCU\_SRAM\_OFFSET can be found in the MCI’s [Top Level Memory Map](#top-level-memory-map).
11291130

@@ -1133,7 +1134,7 @@ The two regions have different access protection. The size of the regions is dyn
11331134
11341135
MCU_SRAM_SIZE_KB = 512 (512KB)
11351136
1136-
bits = $clog2(2097152 + ((512 * 1024) - 1)
1137+
bits = $clog2(12582912 + ((512 * 1024) - 1))
11371138
11381139
bits = 24
11391140

‎src/integration/rtl/caliptra_ss_includes.svh‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,7 @@ parameter CPTRA_SS_ROM_MEM_ADDR_W = $clog2(CPTRA_SS_ROM_DEPTH);
3131
// Interrupt Assignments
3232
// NOTE Vector 0 is reserved by VeeR
3333
`define VEER_INTR_VEC_MCI 1
34-
`define VEER_INTR_VEC_CLP_MBOX_DATA_AVAIL 2
35-
`define VEER_INTR_VEC_I3C 3
36-
`define VEER_INTR_VEC_FC 4
37-
`define VEER_INTR_EXT_LSB 5
34+
`define VEER_INTR_VEC_I3C 2
35+
`define VEER_INTR_EXT_LSB 3
3836

3937
`endif // CPTRA_SS_INCLUDES_SVH

‎src/integration/rtl/caliptra_ss_top.sv‎

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -159,10 +159,11 @@ module caliptra_ss_top
159159
`endif
160160

161161
// Caliptra SS MCU
162-
input logic [31:0] cptra_ss_strap_mcu_lsu_axi_user_i,
163-
input logic [31:0] cptra_ss_strap_mcu_ifu_axi_user_i,
164-
input logic [31:0] cptra_ss_strap_mcu_sram_config_axi_user_i,
165-
input logic [31:0] cptra_ss_strap_mci_soc_config_axi_user_i,
162+
input logic [31:0] cptra_ss_strap_mcu_lsu_axi_user_i,
163+
input logic [31:0] cptra_ss_strap_mcu_ifu_axi_user_i,
164+
input logic [31:0] cptra_ss_strap_mcu_sram_config_axi_user_i,
165+
input logic [31:0] cptra_ss_strap_mci_soc_config_axi_user_i,
166+
output logic cptra_ss_cpu_halt_status_o,
166167

167168
// Caliptra SS MCI MCU SRAM Interface (SRAM, MBOX0, MBOX1)
168169
mci_mcu_sram_if.request cptra_ss_mci_mcu_sram_req_if,
@@ -260,6 +261,7 @@ module caliptra_ss_top
260261
logic mcu_dccm_ecc_single_error;
261262
logic mcu_dccm_ecc_double_error;
262263

264+
logic i3c_irq_o;
263265
logic i3c_peripheral_reset;
264266
logic i3c_escalated_reset;
265267

@@ -271,7 +273,6 @@ module caliptra_ss_top
271273
logic jtag_tdo;
272274
logic i_cpu_halt_req;
273275
logic o_cpu_halt_ack;
274-
logic o_cpu_halt_status;
275276
logic o_cpu_run_ack;
276277

277278
logic [63:0] dma_hrdata ;
@@ -361,7 +362,7 @@ module caliptra_ss_top
361362
logic [31:0] mci_mcu_nmi_vector;
362363
logic mci_mcu_timer_int;
363364

364-
logic [lc_ctrl_reg_pkg::NumAlerts-1:0] lc_alerts_o; // FIXME: This needs to be an input of MCI
365+
logic [lc_ctrl_reg_pkg::NumAlerts-1:0] lc_alerts_o;
365366

366367
// ----------------- FC to Caliptra-Core ports -----------------------
367368
otp_ctrl_part_pkg::otp_broadcast_t from_otp_to_clpt_core_broadcast; // This is a struct data type
@@ -559,23 +560,21 @@ module caliptra_ss_top
559560

560561
//Interrupt connections
561562
assign ext_int[`VEER_INTR_VEC_MCI] = mci_intr;
562-
assign ext_int[`VEER_INTR_VEC_CLP_MBOX_DATA_AVAIL] = mailbox_data_avail;
563-
assign ext_int[`VEER_INTR_VEC_I3C] = 0;
564-
assign ext_int[`VEER_INTR_VEC_FC] = intr_otp_operation_done;
563+
assign ext_int[`VEER_INTR_VEC_I3C] = i3c_irq_o;
565564
assign ext_int[pt.PIC_TOTAL_INT:`VEER_INTR_EXT_LSB] = cptra_ss_mcu_ext_int;
566565

567566
//Aggregate error connections
568567
assign agg_error_fatal[5:0] = {5'b0, cptra_error_fatal}; //CPTRA
569568
assign agg_error_fatal[11:6] = {5'b0, mcu_dccm_ecc_double_error}; //MCU
570569
assign agg_error_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
571-
assign agg_error_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
570+
assign agg_error_fatal[23:18] = {fc_intr_otp_error, fc_alerts}; //FC
572571
assign agg_error_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
573572
assign agg_error_fatal[31:30] = '0; //spare
574573

575574
assign agg_error_non_fatal[5:0] = {5'b0, cptra_error_non_fatal}; //CPTRA
576575
assign agg_error_non_fatal[11:6] = {5'b0, mcu_dccm_ecc_single_error}; //MCU
577576
assign agg_error_non_fatal[17:12] = {{6-lc_ctrl_reg_pkg::NumAlerts{1'b0}}, lc_alerts_o}; //LCC
578-
assign agg_error_non_fatal[23:18] = {{6-otp_ctrl_reg_pkg::NumAlerts{1'b0}}, fc_alerts}; //FC
577+
assign agg_error_non_fatal[23:18] = {fc_intr_otp_error, fc_alerts}; //FC
579578
assign agg_error_non_fatal[29:24] = {4'b0, i3c_peripheral_reset, i3c_escalated_reset}; //I3C
580579
assign agg_error_non_fatal[31:30] = '0; //spare
581580

@@ -803,7 +802,7 @@ module caliptra_ss_top
803802

804803
.i_cpu_halt_req ( i_cpu_halt_req ), // Async halt req to CPU
805804
.o_cpu_halt_ack ( o_cpu_halt_ack ), // core response to halt
806-
.o_cpu_halt_status ( o_cpu_halt_status ), // 1'b1 indicates core is halted
805+
.o_cpu_halt_status ( cptra_ss_cpu_halt_status_o ), // 1'b1 indicates core is halted
807806
.i_cpu_run_req ( 1'b0 ), // Async restart req to CPU
808807
.o_cpu_run_ack ( o_cpu_run_ack ), // Core response to run req
809808

@@ -933,9 +932,8 @@ module caliptra_ss_top
933932
.peripheral_reset_o(i3c_peripheral_reset),
934933
.peripheral_reset_done_i(1'b1),
935934
.escalated_reset_o(i3c_escalated_reset),
936-
.irq_o()
935+
.irq_o(i3c_irq_o)
937936

938-
// TODO: Add interrupts
939937
);
940938

941939
//=========================================================================
@@ -1020,10 +1018,14 @@ module caliptra_ss_top
10201018
.strap_mcu_reset_vector(cptra_ss_strap_mcu_reset_vector_i),
10211019

10221020
.mcu_reset_vector(reset_vector),
1021+
1022+
// OTP
1023+
.intr_otp_operation_done,
1024+
10231025
// MCU Halt Signals
10241026
.mcu_cpu_halt_req_o (i_cpu_halt_req ),
10251027
.mcu_cpu_halt_ack_i (o_cpu_halt_ack ),
1026-
.mcu_cpu_halt_status_i(o_cpu_halt_status),
1028+
.mcu_cpu_halt_status_i(cptra_ss_cpu_halt_status_o),
10271029

10281030
.mcu_no_rom_config(cptra_ss_mcu_no_rom_config_i),
10291031

@@ -1208,7 +1210,7 @@ module caliptra_ss_top
12081210
.prim_generic_otp_inputs_o (cptra_ss_fuse_macro_inputs_o),
12091211

12101212
.intr_otp_operation_done_o (intr_otp_operation_done),
1211-
.intr_otp_error_o (fc_intr_otp_error), //TODO: This signal should be connected to MCI
1213+
.intr_otp_error_o (fc_intr_otp_error),
12121214
// .alert_rx_i (),
12131215
// .alert_tx_o (),
12141216
.alerts(fc_alerts),

‎src/integration/rtl/soc_address_map.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7784,6 +7784,8 @@
77847784
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX0_SOC_REQ_LOCK_EN_MASK (0x1000)
77857785
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_LOW (13)
77867786
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_MASK (0x2000)
7787+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_LOW (14)
7788+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_MASK (0x4000)
77877789
#endif
77887790
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R (0x21001010)
77897791
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R
@@ -7984,6 +7986,8 @@
79847986
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_SOC_REQ_LOCK_STS_MASK (0x1000)
79857987
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_LOW (13)
79867988
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_MASK (0x2000)
7989+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_LOW (14)
7990+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_MASK (0x4000)
79877991
#endif
79887992
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R (0x21001028)
79897993
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R
@@ -8168,6 +8172,8 @@
81688172
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX0_SOC_REQ_LOCK_TRIG_MASK (0x1000)
81698173
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_LOW (13)
81708174
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_MASK (0x2000)
8175+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_LOW (14)
8176+
#define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_MASK (0x4000)
81718177
#endif
81728178
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R (0x21001038)
81738179
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R
@@ -8573,6 +8579,10 @@
85738579
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R
85748580
#define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R (0x12b4)
85758581
#endif
8582+
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R (0x210012b8)
8583+
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R
8584+
#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R (0x12b8)
8585+
#endif
85768586
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x21001300)
85778587
#ifndef MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R
85788588
#define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (0x1300)
@@ -9077,6 +9087,12 @@
90779087
#define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0)
90789088
#define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (0x1)
90799089
#endif
9090+
#define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R (0x21001450)
9091+
#ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R
9092+
#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R (0x1450)
9093+
#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0)
9094+
#define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_MASK (0x1)
9095+
#endif
90809096
#define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR (0x21010000)
90819097
#define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_STATUS (0x21010000)
90829098
#ifndef MCU_TRACE_BUFFER_CSR_STATUS

‎src/integration/rtl/soc_address_map_defines.svh‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -701,6 +701,7 @@
701701
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_R (32'h210012ac)
702702
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX0_SOC_REQ_LOCK_INTR_COUNT_R (32'h210012b0)
703703
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R (32'h210012b4)
704+
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R (32'h210012b8)
704705
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h21001300)
705706
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_MBOX0_ECC_UNC_INTR_COUNT_INCR_R (32'h21001304)
706707
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR_MBOX1_ECC_UNC_INTR_COUNT_INCR_R (32'h21001308)
@@ -785,6 +786,7 @@
785786
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_SCAN_MODE_INTR_COUNT_INCR_R (32'h21001444)
786787
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX0_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'h21001448)
787788
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R (32'h2100144c)
789+
`define SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R (32'h21001450)
788790
`define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR (32'h21010000)
789791
`define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_STATUS (32'h21010000)
790792
`define SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_CONFIG (32'h21010004)

‎src/integration/rtl/soc_address_map_field_defines.svh‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7194,6 +7194,8 @@
71947194
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX0_SOC_REQ_LOCK_EN_MASK (32'h1000)
71957195
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_LOW (13)
71967196
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_MBOX1_SOC_REQ_LOCK_EN_MASK (32'h2000)
7197+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_LOW (14)
7198+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R_NOTIF_OTP_OPERATION_DONE_EN_MASK (32'h4000)
71977199
`endif
71987200
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R
71997201
`define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_EN_R (32'h1010)
@@ -7388,6 +7390,8 @@
73887390
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_SOC_REQ_LOCK_STS_MASK (32'h1000)
73897391
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_LOW (13)
73907392
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX1_SOC_REQ_LOCK_STS_MASK (32'h2000)
7393+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_LOW (14)
7394+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_OTP_OPERATION_DONE_STS_MASK (32'h4000)
73917395
`endif
73927396
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R
73937397
`define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTERNAL_INTR_R (32'h1028)
@@ -7568,6 +7572,8 @@
75687572
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX0_SOC_REQ_LOCK_TRIG_MASK (32'h1000)
75697573
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_LOW (13)
75707574
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_MBOX1_SOC_REQ_LOCK_TRIG_MASK (32'h2000)
7575+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_LOW (14)
7576+
`define MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_TRIG_R_NOTIF_OTP_OPERATION_DONE_TRIG_MASK (32'h4000)
75717577
`endif
75727578
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R
75737579
`define MCI_REG_INTR_BLOCK_RF_NOTIF1_INTR_TRIG_R (32'h1038)
@@ -7888,6 +7894,9 @@
78887894
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R
78897895
`define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_R (32'h12b4)
78907896
`endif
7897+
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R
7898+
`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_R (32'h12b8)
7899+
`endif
78917900
`ifndef MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R
78927901
`define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R (32'h1300)
78937902
`define MCI_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_COUNT_INCR_R_PULSE_LOW (0)
@@ -8308,6 +8317,11 @@
83088317
`define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_LOW (0)
83098318
`define MCI_REG_INTR_BLOCK_RF_NOTIF_MBOX1_SOC_REQ_LOCK_INTR_COUNT_INCR_R_PULSE_MASK (32'h1)
83108319
`endif
8320+
`ifndef MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R
8321+
`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R (32'h1450)
8322+
`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_LOW (0)
8323+
`define MCI_REG_INTR_BLOCK_RF_NOTIF_OTP_OPERATION_DONE_INTR_COUNT_INCR_R_PULSE_MASK (32'h1)
8324+
`endif
83118325
`ifndef MCU_TRACE_BUFFER_CSR_STATUS
83128326
`define MCU_TRACE_BUFFER_CSR_STATUS (32'h0)
83138327
`define MCU_TRACE_BUFFER_CSR_STATUS_WRAPPED_LOW (0)

‎src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,12 @@ contents:
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- ../test_suites/smoke_test_mcu_sram_protected_region/smoke_test_mcu_sram_protected_region.yml
2727
- ../test_suites/smoke_test_mcu_sram_execution_region/smoke_test_mcu_sram_execution_region.yml
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- ../test_suites/smoke_test_mcu_sram_execution_region/smoke_test_mcu_sram_execution_region_max_size.yml
29+
- ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer.yml
30+
- ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_single.yml
31+
- ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_random.yml
32+
- ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_64.yml
33+
- ../test_suites/smoke_test_mcu_trace_buffer/smoke_test_mcu_trace_buffer_63.yml
34+
- ../test_suites/smoke_test_mcu_trace_buffer_no_debug/smoke_test_mcu_trace_buffer_no_debug.yml
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- ../test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox0_valid_user.yml
3036
- ../test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox0_write_user_lock.yml
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- ../test_suites/smoke_test_mcu_mbox_usr_lock_out_zero/smoke_test_mcu_mbox0_usr_lock_out_zero.yml

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