Merge remote-tracking branch 'chips/main' into caliptra_ss-synthesis-build-fix-nvidia

Author: calebofearth

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docs/CaliptraSSHardwareSpecification.md

@@ -1321,6 +1321,22 @@ MCI aggregates the error information (Fatal, Non-Fatal errors from Caliptra, any
 
 ![](images/MCI-error-agg.png)
 
+Aggregate error register assignments are documented in the register specification: **TODO:** Add a link to rdl -> html file
+
+Regions of 6 bits in the aggregate error registers are reserved for each component.
+MCU and Caliptra errors are connected to appropriate severity levels.
+Lifecycle controller, fuse controller and I3C are connected to both severities. 
+Masks are used to set the severity of each error for these components. These can be configured by integrators, ROM, or runtime firmware.
+
+| **Error Register Bits** | **Component**         | **Default Error Severity** | **Description**          |
+| :---------              | :---------            | :---------                 |:---------                |
+| Aggregate error[5:0]    | Caliptra core         | Both                       | [Caliptra errors](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md#error-reporting-and-handling) |
+| Aggregate error[11:6]   | MCU                   | Both                       | DCCM double bit ECC error is fatal <br> DCCM single bit ECC error is non-fatal |
+| Aggregate error[17:12]  | Life cycle controller | Fatal                      | [LCC alerts](https://opentitan.org/book/hw/ip/lc_ctrl/doc/interfaces.html#security-alerts) |
+| Aggregate error[23:18]  | OTP Fuse controller   | Fatal                      | [FC alerts](https://opentitan.org/book/hw/top_earlgrey/ip_autogen/otp_ctrl/doc/interfaces.html#security-alerts) |
+| Aggregate error[29:24]  | I3C                   | Non-Fatal                  | Peripheral reset and escalated reset pins from I3C <br> **TODO:** Add a link to I3C doc |
+| Aggregate error[31:30]  | Spare bits            | None                       | Spare bits for integrator use |
+
 MCI also generates error signals for its own internal blocks, specifically for MCU SRAM & mailboxes double bit ECC and WDT.
 
 ![](images/MCI-internal-error.png)