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1 change: 0 additions & 1 deletion docs/CaliptraSSIntegrationSpecification.md
Original file line number Diff line number Diff line change
Expand Up @@ -316,7 +316,6 @@ File at path includes parameters and defines for Caliptra Subystem `src/integrat
| External | output | 1 | `cptra_ss_cptra_core_etrng_req_o` | External TRNG request output |
| External | input | 4 | `cptra_ss_cptra_core_itrng_data_i` | Internal TRNG data input |
| External | input | 1 | `cptra_ss_cptra_core_itrng_valid_i` | Internal TRNG valid input |
| External | interface | na | `cptra_ss_mcu_rom_macro_req_if` | MCU ROM macro request interface |
| External | interface | na | `cptra_ss_mci_mcu_sram_req_if` | MCI MCU SRAM request interface |
| External | interface | na | `cptra_ss_mci_mbox0_sram_req_if` | MCI mailbox 0 SRAM request interface |
| External | interface | na | `cptra_ss_mci_mbox1_sram_req_if` | MCI mailbox 1 SRAM request interface |
Expand Down
9 changes: 0 additions & 9 deletions src/integration/rtl/caliptra_ss_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -126,9 +126,6 @@ module caliptra_ss_top
input logic cptra_ss_cptra_core_itrng_valid_i,
`endif

// Caliptra SS MCU ROM Macro Interface
mci_mcu_sram_if.request cptra_ss_mcu_rom_macro_req_if, // MCU ROM interface

// Caliptra SS MCU
input logic [CPTRA_SS_MCU_USER_WIDTH-1:0] cptra_ss_strap_mcu_lsu_axi_user_i,
input logic [CPTRA_SS_MCU_USER_WIDTH-1:0] cptra_ss_strap_mcu_ifu_axi_user_i,
Expand Down Expand Up @@ -1101,12 +1098,6 @@ module caliptra_ss_top
.s_mem_req_if(mcu_rom_mem_export_if)
);

always_comb begin
cptra_ss_mcu_rom_macro_req_if.req = '0;
cptra_ss_mcu_rom_mbox0_sram_req_if.req = '0;
cptra_ss_mcu_rom_mbox1_sram_req_if.req = '0;
end

//=========================================================================
// MCI Instance
//=========================================================================
Expand Down
25 changes: 0 additions & 25 deletions src/integration/testbench/caliptra_ss_top_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -1170,11 +1170,6 @@ module caliptra_ss_top_tb
assign axi_interconnect.sintf_arr[1].RLAST = cptra_ss_i3c_s_axi_if.rlast;
assign cptra_ss_i3c_s_axi_if.rready = axi_interconnect.sintf_arr[1].RREADY;

mci_mcu_sram_if cptra_ss_mcu_rom_macro_req_if (
.clk(core_clk),
.rst_b(rst_l)
);

mci_mcu_sram_if #(
.ADDR_WIDTH(MCU_SRAM_ADDR_WIDTH)
) cptra_ss_mci_mcu_sram_req_if (
Expand Down Expand Up @@ -1466,23 +1461,6 @@ module caliptra_ss_top_tb
assign cptra_ss_mcu_rom_s_axi_if.rready = axi_interconnect.sintf_arr[2].RREADY;


// mci_sram #(
// .DEPTH (18'h0_7FFF), // 64KB -- FIXME (need to update this value)
// .DATA_WIDTH(39),
// .ADDR_WIDTH(32)
// ) imem (
// .clk_i (core_clk),
//
// .cs_i (cptra_ss_mcu_rom_macro_req_if.req.cs),
// .we_i (cptra_ss_mcu_rom_macro_req_if.req.we),
// .addr_i ({14'h0, cptra_ss_mcu_rom_macro_req_if.req.addr, 2'b0}),
// .wdata_i (cptra_ss_mcu_rom_macro_req_if.req.wdata),
// .rdata_o (cptra_ss_mcu_rom_macro_req_if.resp.rdata)
// );
always_comb begin
cptra_ss_mcu_rom_macro_req_if.resp.rdata = '0;
end

rom #(
.DEPTH (16'h7FFF), // 64KB
.DATA_WIDTH(64),
Expand Down Expand Up @@ -1830,9 +1808,6 @@ module caliptra_ss_top_tb
.cptra_ss_strap_cptra_axi_user_i,
.cptra_ss_strap_debug_axi_user_i,

//MCU ROM
.cptra_ss_mcu_rom_macro_req_if,

//MCI
.cptra_ss_mci_mcu_sram_req_if,
.cptra_ss_mci_mbox0_sram_req_if,
Expand Down
2 changes: 1 addition & 1 deletion third_party/caliptra-rtl
Submodule caliptra-rtl updated 471 files