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clayton8
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Mar 13, 2025
clayton8
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- New MCU MBOX required due to new "third party" access called "Target" user in the spec
- MCU MBOX SRAM is now fully addressable and has a TARGET_USER programmed by MCU
- Added MCU MBOX SRAMs to the TB
SOC IFC MBOX feature set does not match MCI's needs, so a new mailbox was needed with a similar feature set. The major difference is that the SRAM is fully addressable, a new target user, and the interrupts are slightly different.
Need to avoid Target User being unset by MCU and an SOC agent having 0x0 AXI User getting inadvertant access to the mailbox.
MCI was looking at entire AXI address instead of only the internal address bits meaning the MBOXes could never be accessed.
The MCI address map chaned with the new MCU Mailbox. This caused issues with our linker file and how we compiled and preloaded the MCU SRAM.
MCU MBOX addressing was wrongly implemented assuming address width was 21 bits. In reality it is 22 bits which forces it to be aligned to a 0x40_0000 boundary.
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Pull Request Overview
This PR adds a new MCU mailbox design with expanded functionalities including a Target user, fully addressable SRAM, and dedicated error and interrupt handling, as well as updating the corresponding testbench and compile configuration.
- Updated hardware specification documentation with detailed MCU mailbox components and behaviors.
- Added new compile configuration entries for mailbox RTL files.
Reviewed Changes
Copilot reviewed 35 out of 35 changed files in this pull request and generated 7 comments.
| File | Description |
|---|---|
| docs/CaliptraSSHardwareSpecification.md | Added new sections for mailbox features, locking, errors, and address mapping. |
| src/mci/config/compile.yml | Included new mailbox related RTL source files in compile targets. |
Comments suppressed due to low confidence (1)
docs/CaliptraSSHardwareSpecification.md:1050
- Typo detected: "availalbe" should be "available".
| Mailbox data available from SOC | Asserted when MCU gets lock and assert the EXECUTE register, indicating data is availalbe for MCU.
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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Pull Request Overview
This PR adds support for a new MCU Mailbox in both the hardware specification and RTL build configuration, enabling a new "Target" user access mode and fully addressing the SRAM in the mailbox.
- Updated the hardware specification to include new MCU Mailbox sections (e.g., Target User, Locking, Fully Addressable SRAM).
- Detailed new error conditions and interactions for mailbox usage and trusted/untrusted AXI users.
- Updated compile configuration to include the new RTL sources for MCU Mailbox functionality.
Reviewed Changes
Copilot reviewed 35 out of 35 changed files in this pull request and generated 5 comments.
| File | Description |
|---|---|
| docs/CaliptraSSHardwareSpecification.md | Added new MCU Mailbox sections and updated descriptions in the spec. |
| src/mci/config/compile.yml | Included new RTL files for the MCU Mailbox feature in the build config. |
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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Pull Request Overview
This PR adds a new MCU Mailbox (MBOX) design and hardware specification to support “third party” access, introducing additional features such as a fully addressable SRAM and a TARGET_USER controlled by the MCU. Key changes include:
- Expanded documentation within CaliptraSSHardwareSpecification.md covering new mailbox features and error handling.
- Updates to the compile configuration to include new MCU mailbox source files.
Reviewed Changes
Copilot reviewed 35 out of 35 changed files in this pull request and generated 1 comment.
| File | Description |
|---|---|
| docs/CaliptraSSHardwareSpecification.md | Added sections detailing new MCU Mailbox features including limited trusted AXI users, locking, target user, SRAM clearing, interrupts, errors, and address map. |
| src/mci/config/compile.yml | Updated to include new mailbox related source files in the targets and RTL sections. |
Comments suppressed due to low confidence (1)
docs/CaliptraSSHardwareSpecification.md:1016
- [nitpick] The anchor link 'mcu-mailbox-limited-trusted-AXI-user' is inconsistent with the plural form used elsewhere; consider updating it to '#mcu-mailbox-limited-trusted-axi-users' for consistency.
Target users must be an [MCU Mailbox trusted user](mcu-mailbox-limited-trusted-AXI-user)
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
…dress. RDL had MCU SRAM correctly mapped to 0xC0_0000 but RTL and linker files had it mapped to 0xA0_0000. Due to size of SRAM and MBOX SRAMs it must start at 0xC0_0000. mcu_cptra_bringup.c had MCU SRAM address hard coded instead of using *.h file generated by RDL.
…iptra-ss into ckuchta-mcu-mbox
…imestamp and hash after successful run
…iptra-ss into ckuchta-mcu-mbox
…imestamp and hash after successful run
Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com>
clayton8
changed the title
During a warm reset data can leak via the SRAM. To prevent this we are giving MCU the MBOX after MCI reset is released and the MCU needs to set up DLEN and release the MBOX causing the SRAM to be zeroed out.
…iptra-ss into ckuchta-mcu-mbox
…imestamp and hash after successful run
calebofearth
previously approved these changes
Mar 14, 2025
Avoid using the rst_b in combinational logic.
…iptra-ss into ckuchta-mcu-mbox
…imestamp and hash after successful run
Nitsirks
approved these changes
Mar 14, 2025
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