[TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist)

src/integration/config/avery_vip.vf

@@ -25,6 +25,9 @@ ${AVERY_SIM}/src/avery_pkg_test.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg_xactor.sv
 ${AVERY_AXI}/src.axi/aaxi_class_pll.sv
+${AVERY_AXI}/checker/monitor_wrapper/BP063/aaxi_monitor_wrapper.sv
+${AVERY_AXI}/src.VCS/aaxi_busmonitor.v
+${AVERY_AXI}/src.axi/aaxi_coverage_metrics.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg_test.sv
 ${AVERY_AXI}/src.axi/aaxi_intf.sv
 ${AVERY_I3C}/src/ai2c_pkg.sv

src/integration/config/caliptra_ss_top_tb.vf

@@ -103,6 +103,7 @@
 +incdir+${AVERY_I3C}/testsuite.i3c/dut_master_stby
 +incdir+${AVERY_I3C}/testbench
 +incdir+${CALIPTRA_SS_ROOT}/src/mci/coverage
++incdir+${CALIPTRA_SS_ROOT}/src/integration/coverage
 +incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench
 +incdir+${CALIPTRA_SS_ROOT}/src/integration/testbench/sv_tests/ai3c
 ${CALIPTRA_SS_ROOT}/third_party/caliptra-rtl/src/integration/rtl/config_defines.svh
@@ -891,6 +892,9 @@ ${AVERY_SIM}/src/avery_pkg_test.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg_xactor.sv
 ${AVERY_AXI}/src.axi/aaxi_class_pll.sv
+${AVERY_AXI}/checker/monitor_wrapper/BP063/aaxi_monitor_wrapper.sv
+${AVERY_AXI}/src.VCS/aaxi_busmonitor.v
+${AVERY_AXI}/src.axi/aaxi_coverage_metrics.sv
 ${AVERY_AXI}/src.axi/aaxi_pkg_test.sv
 ${AVERY_AXI}/src.axi/aaxi_intf.sv
 ${AVERY_I3C}/src/ai2c_pkg.sv
@@ -901,6 +905,9 @@ ${CALIPTRA_SS_ROOT}/src/mci/coverage/mci_top_cov_if.sv
 ${CALIPTRA_SS_ROOT}/src/mci/coverage/mci_top_cov_bind.sv
 ${CALIPTRA_SS_ROOT}/src/lc_ctrl/coverage/lc_ctrl_cov_if.sv
 ${CALIPTRA_SS_ROOT}/src/lc_ctrl/coverage/lc_ctrl_cov_bind.sv
+${CALIPTRA_SS_ROOT}/src/integration/coverage/caliptra_ss_top_cov_if.sv
+${CALIPTRA_SS_ROOT}/src/integration/coverage/caliptra_ss_top_cov_props.sv
+${CALIPTRA_SS_ROOT}/src/integration/coverage/caliptra_ss_top_cov_bind.sv
 ${CALIPTRA_SS_ROOT}/src/integration/testbench/tb_top_pkg.sv
 ${CALIPTRA_SS_ROOT}/src/integration/testbench/axi_slv.sv
 ${CALIPTRA_SS_ROOT}/src/integration/testbench/mci_sram.sv

src/integration/config/compile.yml

@@ -38,6 +38,9 @@ targets:
       - $AVERY_AXI/src.axi/aaxi_pkg.sv
       - $AVERY_AXI/src.axi/aaxi_pkg_xactor.sv
       - $AVERY_AXI/src.axi/aaxi_class_pll.sv
+      - $AVERY_AXI/checker/monitor_wrapper/BP063/aaxi_monitor_wrapper.sv
+      - $AVERY_AXI/src.VCS/aaxi_busmonitor.v
+      - $AVERY_AXI/src.axi/aaxi_coverage_metrics.sv 
       - $AVERY_AXI/src.axi/aaxi_pkg_test.sv
       - $AVERY_AXI/src.axi/aaxi_intf.sv
       #-- I3C VIP
@@ -100,6 +103,21 @@ targets:
       - $COMPILE_ROOT/rtl/caliptra_ss_top_w_stub.sv
     tops: [caliptra_ss_top_w_stub]
 --- 
+provides: [caliptra_ss_top_tb_coverage]
+schema_version: 2.4.0
+requires:
+  - axi_dma_coverage
+  - mci_coverage
+  - lc_ctrl_coverage
+targets:
+  tb:
+    directories:
+      - $COMPILE_ROOT/coverage
+    files:
+      - $COMPILE_ROOT/coverage/caliptra_ss_top_cov_if.sv
+      - $COMPILE_ROOT/coverage/caliptra_ss_top_cov_props.sv
+      - $COMPILE_ROOT/coverage/caliptra_ss_top_cov_bind.sv
+--- 
 provides: [caliptra_ss_top_tb]
 schema_version: 2.4.0
 requires:
@@ -113,8 +131,7 @@ requires:
   - fuse_ctrl_pkg
   - caliptra_top_tb_pkg
   - avery_vip
-  - mci_coverage
-  - lc_ctrl_coverage
+  - caliptra_ss_top_tb_coverage
 targets:
   tb:
     directories:
@@ -143,6 +160,7 @@ targets:
     pre_exec: 'echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/ecc/tb/ecc_secp384r1.exe . 
                 && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/doe/tb/doe_test_gen.py .
                 && echo "[PRE-EXEC] Copying SHA256 wntz vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/sha256/tb/sha256_wntz_test_gen.py .
+                && echo "[PRE-EXEC] Copying SHA512 Vectors to $(pwd)" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/integration/tb/vectors/SHA*.rsp .
                 && echo "[PRE-EXEC] Copying MLDSA vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/submodules/adams-bridge/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5 .
                 && echo "[PRE-EXEC] Copying MLDSA debug vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/submodules/adams-bridge/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug .
                 && echo "[PRE-EXEC] Copying mldsa directed vector to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/mldsa/tb/smoke_test_mldsa_vector.hex .
@@ -155,6 +173,8 @@ global:
         - '-sverilog -full64'
         - '-debug_access+all'
         - +define+CLP_ASSERT_ON
+        - +define+AVERY_ASSERT_ON
+        - +define+AVERY_MONITOR_ON
         # Used in caliptra_top_sva to find signals
         - +define+CPTRA_TB_TOP_NAME=caliptra_ss_top_tb
         - +define+CPTRA_TOP_PATH=caliptra_ss_top_tb.caliptra_ss_dut.caliptra_top_dut

src/mcu/coverage/caliptra_mcu_top_cov_bind.sv → src/integration/coverage/caliptra_ss_top_cov_bind.sv

@@ -13,9 +13,9 @@
 // limitations under the License.
 
 
-module caliptra_mcu_top_cov_bind;
+module caliptra_ss_top_cov_bind;
     `ifdef FCOV
-    bind caliptra_mcu_top caliptra_mcu_top_cov_if i_caliptra_mcu_top_cov_if(.*);
-    bind caliptra_mcu_top caliptra_mcu_top_cov_props i_caliptra_mcu_top_cov_props(.*);
+    bind caliptra_ss_top caliptra_ss_top_cov_if i_caliptra_ss_top_cov_if(.*);
+    bind caliptra_ss_top caliptra_ss_top_cov_props i_caliptra_ss_top_cov_props(.*);
     `endif
 endmodule

src/integration/coverage/caliptra_ss_top_cov_if.sv

@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`ifndef VERILATOR
+
+`include "soc_address_map_defines.svh"
+
+interface caliptra_ss_top_cov_if   
+    import soc_ifc_pkg::*;  
+    (
+    input logic cptra_ss_clk_i,
+    //SoC AXI Interface
+    axi_if cptra_ss_cptra_core_m_axi_if,
+    input logic cptra_ss_rst_b_i,
+    input logic cptra_ss_pwrgood_i
+);
+
+    logic cptra_ss_cptra_core_m_axi_if_ar_hshake;
+    logic cptra_ss_cptra_core_m_axi_if_aw_hshake;
+    always_comb cptra_ss_cptra_core_m_axi_if_ar_hshake = cptra_ss_cptra_core_m_axi_if.arvalid && cptra_ss_cptra_core_m_axi_if.arready;
+    always_comb cptra_ss_cptra_core_m_axi_if_aw_hshake = cptra_ss_cptra_core_m_axi_if.awvalid && cptra_ss_cptra_core_m_axi_if.awready;
+
+    covergroup caliptra_ss_top_cov_grp @(posedge cptra_ss_clk_i);
+        option.per_instance = 1;
+        //-----------------------------------------
+        //AXI Manager Coverpoints
+        //-----------------------------------------
+        axi_rd_txn: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake {
+            bins single_axi_rd_txn = (0 => 1 => 0);
+            bins b2b_axi_rd_txn = (1 [*5]); //5 rd txns in a row
+        }
+        axi_rd_rsp: coverpoint cptra_ss_cptra_core_m_axi_if.rvalid && cptra_ss_cptra_core_m_axi_if.rready {
+            bins axi_rd_hshake = {1'b1};
+            bins single_axi_rd_rsp = (0 => 1 => 0);
+        }
+        axi_wr_txn: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake {
+            bins single_axi_wr_txn = (0 => 1 => 0);
+            bins b2b_axi_wr_txn = (1 [*5]); //5 wr txns in a row
+        }
+        axi_wr_rsp: coverpoint cptra_ss_cptra_core_m_axi_if.bvalid && cptra_ss_cptra_core_m_axi_if.bready {
+            bins axi_wr_hshake = {1'b1};
+            bins single_axi_wr_rsp = (0 => 1 => 0);
+        }
+        axi_any_txn:coverpoint (cptra_ss_cptra_core_m_axi_if_ar_hshake) || (cptra_ss_cptra_core_m_axi_if_aw_hshake) {
+            bins single_axi_txn = (0 => 1 => 0);
+            bins b2b_axi_txn = (1 [*5]); //5 txns in a row
+        }
+
+        axi_rd_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
+            bins axi_rd_req = {1'b1};
+        }
+        axi_wr_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
+            bins axi_wr_req = {1'b1};
+        }
+        axi_rd_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
+            bins axi_rd_req = {1'b1};
+        }
+        axi_wr_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
+            bins axi_wr_req = {1'b1};
+        }
+        // FIXME replace these magic numbers with some macro once soc_address_map is updated
+        axi_rd_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[64'h7000_0000:64'h7000_03FF]} {
+            bins axi_rd_req = {1'b1};
+        }
+        axi_wr_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[64'h7000_0000:64'h7000_03FF]} {
+            bins axi_wr_req = {1'b1};
+        }
+    endgroup
+    caliptra_ss_top_cov_grp caliptra_ss_top_cov_grp1 = new();
+//    logic clk_gating_en;
+//    logic cpu_halt_status;
+//    logic wdt_timer1_en;
+//    logic wdt_timer2_en;
+//    logic nmi_int;
+//
+//    assign clk_gating_en = caliptra_top.cg.clk_gate_en;
+//    assign cpu_halt_status = caliptra_top.cg.cpu_halt_status;
+//    assign wdt_timer1_en = caliptra_top.soc_ifc_top1.i_wdt.timer1_en;
+//    assign wdt_timer2_en = caliptra_top.soc_ifc_top1.i_wdt.timer2_en;
+//    assign nmi_int = caliptra_top.nmi_int;
+//    
+//
+//    covergroup caliptra_top_cov_grp @(posedge clk);
+//        option.per_instance = 1;
+//
+//        //-----------------------------------------
+//        //WDT coverpoints
+//        //-----------------------------------------
+//        wdt_t1: coverpoint wdt_timer1_en;
+//        wdt_t2: coverpoint wdt_timer2_en;
+//        wdt_t1Xt2: cross wdt_t1, wdt_t2;
+//        // wdt_t1t2Xwarmrst: cross wdt_t1Xt2, cptra_rst_b;
+//        // wdt_t1t2Xcoldrst: cross wdt_t1Xt2, cptra_pwrgood;
+//
+//        //-----------------------------------------
+//        //CLK GATING coverpoints
+//        //-----------------------------------------
+//        axi_rd_txn:         coverpoint s_axi_r_if.arvalid && s_axi_r_if.arready {
+//            bins single_axi_rd_txn = (0 => 1 => 0);
+//            bins b2b_axi_rd_txn = (1 [*5]); //5 rd txns in a row
+//        }
+//        axi_rd_rsp:         coverpoint s_axi_r_if.rvalid && s_axi_r_if.rready {
+//            bins axi_rd_hshake = {1'b1};
+//            bins single_axi_rd_rsp = (0 => 1 => 0);
+//        }
+//        axi_wr_txn:         coverpoint s_axi_w_if.awvalid && s_axi_w_if.awready {
+//            bins single_axi_wr_txn = (0 => 1 => 0);
+//            bins b2b_axi_wr_txn = (1 [*5]); //5 wr txns in a row
+//        }
+//        axi_wr_rsp:         coverpoint s_axi_w_if.bvalid && s_axi_w_if.bready {
+//            bins axi_wr_hshake = {1'b1};
+//            bins single_axi_wr_rsp = (0 => 1 => 0);
+//        }
+//        axi_any_txn:        coverpoint (s_axi_r_if.arvalid && s_axi_r_if.arready) || (s_axi_w_if.awvalid && s_axi_w_if.awready) {
+//            bins single_axi_txn = (0 => 1 => 0);
+//            bins b2b_axi_txn = (1 [*5]); //5 txns in a row
+//        }
+//        cg_en:              coverpoint clk_gating_en;
+//        core_asleep_value:  coverpoint cpu_halt_status;
+//        core_asleep_trans:  coverpoint cpu_halt_status {
+//            bins bin01 = (0 => 1);
+//            bins bin10 = (1 => 0);
+//        }
+//        warm_rst:           coverpoint cptra_rst_b;
+//
+//        scan:               coverpoint scan_mode;
+//        debug:              coverpoint security_state.debug_locked;
+//        fatal_error:        coverpoint cptra_error_fatal;
+//        nmi:                coverpoint nmi_int;
+//        generic:            coverpoint generic_input_wires;
+//
+//        enXcore_asleep:             cross cg_en, core_asleep_value {
+//            ignore_bins b0 = enXcore_asleep with ((cg_en == 0) && (core_asleep_value == 1));
+//        }
+//        enXcore_asleepXwarm_rst:    cross enXcore_asleep, warm_rst;
+//        enXcore_asleepXcold_rst:    cross enXcore_asleep, cptra_pwrgood;
+//        // {
+//        //     ignore_bins b0 = enXcore_asleepXwarm_rst with ((cg_en == 1) && (core_asleep_value == 1) && (warm_rst == 0));
+//        // }
+//        enXcore_asleepXwdt1:        cross enXcore_asleep, wdt_t1;
+//        enXcore_asleepXwdt2:        cross enXcore_asleep, wdt_t2;
+//
+//        enXcore_asleepXscan:        cross enXcore_asleep, scan;
+//        enXcore_asleepXdebug:       cross enXcore_asleep, debug;
+//        enXcore_asleepXfatalerr:    cross enXcore_asleep, fatal_error;
+//        enXcore_asleepXnmi:         cross enXcore_asleep, nmi;
+//        enXcore_asleepXaxi:         cross enXcore_asleep, axi_any_txn;
+//        enXcore_asleepXgeneric:     cross enXcore_asleep, generic;
+//    endgroup
+//
+//    covergroup generic_input_wires_cg(input logic generic_bit) @(posedge clk);
+//        option.per_instance = 1;
+//        value:      coverpoint generic_bit;
+//        transition: coverpoint generic_bit {
+//            bins bin01 = (0 => 1);
+//            bins bin10 = (1 => 0);
+//        }
+//    endgroup
+//
+//    // CLK_GATING_cov_grp CLK_GATING_cov_grp1 = new();
+//    // WDT_cov_grp WDT_cov_grp1 = new();
+//    caliptra_top_cov_grp caliptra_top_cov_grp1 = new();
+//    
+//    generic_input_wires_cg giw_cg[64];
+//    //foreach(giw_cg[i]) giw_cg[i] = new(generic_input_wires[i]);
+//    initial begin
+//        for(int i = 0; i < 64; i++) begin
+//            giw_cg[i] = new(generic_input_wires[i]);
+//        end
+//    end
+
+endinterface
+
+`endif

src/integration/coverage/caliptra_ss_top_cov_props.sv

@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// This file contains properties that define various sequences of events in KV
+
+module caliptra_ss_top_cov_props();
+
+    `ifndef VERILATOR
+
+            //------------------------------------------------------------------------------
+            //Check that WDT was enabled before issuing warm reset
+            //------------------------------------------------------------------------------
+//            property cover_prop_wdt_t1_warmrst;
+//                @(posedge soc_ifc_top1.i_wdt.clk)
+//                ($rose(soc_ifc_top1.i_wdt.timer1_en) |-> ##[0:$] !soc_ifc_top1.i_wdt.cptra_rst_b);
+//            endproperty
+//            covprop_wdt_t1_warmrst: cover property(cover_prop_wdt_t1_warmrst);
+//
+//            property cover_prop_wdt_t2_warmrst;
+//                @(posedge soc_ifc_top1.i_wdt.clk)
+//                ($rose(soc_ifc_top1.i_wdt.timer2_en) |-> ##[0:$] !soc_ifc_top1.i_wdt.cptra_rst_b);
+//            endproperty
+//            covprop_wdt_t2_warmrst: cover property(cover_prop_wdt_t2_warmrst);
+//
+//            //------------------------------------------------------------------------------
+//            //Check that locks/clear were set before issuing cold reset
+//            //------------------------------------------------------------------------------
+//            property cover_prop_wdt_t1_coldrst;
+//                @(posedge soc_ifc_top1.clk)
+//                ($rose(soc_ifc_top1.i_wdt.timer1_en) |=> ##[0:$] !soc_ifc_top1.cptra_pwrgood);
+//            endproperty
+//            covprop_wdt_t1_coldrst: cover property(cover_prop_wdt_t1_coldrst);
+//
+//            property cover_prop_wdt_t2_coldrst;
+//                @(posedge soc_ifc_top1.clk)
+//                ($rose(soc_ifc_top1.i_wdt.timer2_en) |=> ##[0:$] !soc_ifc_top1.cptra_pwrgood);
+//            endproperty
+//            covprop_wdt_t2_coldrst: cover property(cover_prop_wdt_t2_coldrst);
+
+    `endif
+
+endmodule

src/integration/stimulus/L1_Nightly_Directed_caliptra_ss_top_tb_regression.yml

@@ -6,7 +6,7 @@ contents:
       tags: ["L1", "caliptra_ss_top_tb", "Directed", "Nightly"]
       path: ""
       weight: 100
-      generations: 130
+      generations: 150
       formats:
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"

src/integration/stimulus/L1_Nightly_Random_caliptra_ss_top_tb_regression.yml

@@ -6,11 +6,13 @@ contents:
       tags: ["L1", "caliptra_ss_top_tb", "Random", "Nightly"]
       path: ""
       weight: 100
-      generations: 30
+      generations: 50
       formats:
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
       templates:
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_fc_random_item_prov/smoke_test_fc_random_item_prov: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_RMA/smoke_test_lcc_RMA: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_test_unlocked0_prov/caliptra_ss_fuse_ctrl_test_unlocked0_prov: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_unexpected_reset/caliptra_ss_fuse_ctrl_unexpected_reset: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha: { weight: 100 }

src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv

@@ -28,4 +28,5 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_unexpected_r
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_valid_user/smoke_test_mcu_mbox_valid_user                             , None           , None          , L0  , None, caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_write_user_lock/smoke_test_mcu_mbox_write_user_lock                   , None           , None          , L0  , None, caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_kmac_kat/smoke_test_lcc_kmac_kat                                           , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, Promote        , None     , 100
-$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans                                         , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans                                         , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha                                   , Random         , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100