[RTL][DOC] Update MCI RESET_RESON register and add HITLESS flows to spec#235
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[RTL][DOC] Update MCI RESET_RESON register and add HITLESS flows to spec#235
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clayton8
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Apr 3, 2025
clayton8
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- RESET_REASON is mostly FW controlled for greater flexibility in design. Caliptra should be updating this register on all MCU FW update
- Add all hitless update flows for MCU/MCI
- Add warm reset restrictions to spec
* [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com>
…n script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226)
* [fuse_ctrl, script] Move to common directory
This commit moves the gen_fuse_ctrl_partitions scripts to a common
fuse_ctrl_script directory such that the lib can be reused by other scripts.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [fuse_ctrl, script] Add VMEM generation script
This commit adds a script that generated VMEM files that can be loaded
into the fuse controller. The life cycle state, counter, and the
transition token can be programed by using cmd line arguments.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, lib] Extend lc_ctrl library
This commit adds functions to the lc_ctrl library
that could be useful for different tests.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] LCC transition test
This commit adds a simple LCC transition test. The test reads
the current LCC state and tries to jump into the next one.
By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py
different starting LC states and unlock tokens can be tested.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [fuse_ctrl, script] Allow to configure multiple tokens
This commit extends the VMEM generation script such that multiple
tokens can be programmed into OTP vmem.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans
This commit adds a README to guide the user to run the test.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Add smoke_test_lcc_kmac_kat
As the KMAC core is inside the lc_ctrl and there is no direct access for
SW, this test indirectly tests the KMAC output.
- Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from
test_unlock_token.hjson and writes them hashed into the
otp-img.2048.vmem file
- Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens.
The test performs state transitions from TEST_LOCKED0 to
PROD_END.
If the state transition was successful, the unhashed
token was correctly hashed by the KMAC block and
matches the hashed token that was generated by the
SHAKE reference implementation in gen_fuse_ctrl_vmem.py
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [fuse_ctrl, script] Random parameter generation
This commit extends the gen_fuse_ctrl_vmem script such that the
unlock tokens, the LC counter, and LC state can be generated
randomly. Moreover, a C header file can be generated that contains
the unhased tokens that are programmed into VMEM.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Randomly generate unlock tokens
This commit extends the test run script such that the
gen_fuse_ctrl_vmem.py script is used to randomize the
state transition unlock tokens.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans
This test randomizes the caliptra_ss_lcc_st_trans test by calling
the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE
and LC_CNT into the otp vmem file.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Switch mode of tests
- caliptra_ss_lcc_st_trans: Use random LC state & LC counter
but fixed unlock tokens
- smoke_test_lcc_kmac_kat: Use random unlock token but fixed
starting LC state and LC counter
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Switch mode of tests
- caliptra_ss_lcc_st_trans: Use random LC state & LC counter
but fixed unlock tokens
- smoke_test_lcc_kmac_kat: Use random unlock token but fixed
starting LC state and LC counter
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE
This commit adds simple covergroups for the LC counter
value and LC state. Bins are added to make sure that all
possible states and counters have been seen.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask
LC_CTRL.STATUS.READY should be bit 1 in the bit field and
LC_CTRL.STATUS.INIT should be bit 0 in the bit field.
Closes #177
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* updated .vf file
* [script] Add additional python requirements
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl,test] Use error function when expecting an error
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl,test] Use error function when expecting an error
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [lc_ctrl, test] Use PB Random Seed
To generate the randomized OTP VMEM image.
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* added vf files with new sim_tools
---------
Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org>
* [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com>
* Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase
…ted timestamp and hash after successful run
We want the RESET_REASON register to be updated by Caliptra FW instead of all done in HW. This gives greater flexability to the design and will help with any corner cases we may encounter.
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Pull Request Overview
This PR updates the MCI register addresses in the RTL header and expands the documentation to include comprehensive details on MCU FW update flows, including hitless and warm reset update scenarios.
- Updates register base addresses in mci_top.h for proper mapping.
- Introduces new documentation sections and updates existing content for clarity on FW update flows.
Reviewed Changes
Copilot reviewed 3 out of 11 changed files in this pull request and generated 3 comments.
| File | Description |
|---|---|
| src/mci/rtl/mci_top.h | Updates register address definitions to reflect new mapping ranges. |
| docs/CaliptraSSIntegrationSpecification.md | Adds new sections outlining MCU FW update flows and updates the documentation list accordingly. |
| docs/CaliptraSSHardwareSpecification.md | Revises the description of hitless update handshake and register tracking to reference integration documentation. |
Files not reviewed (8)
- src/mci/rtl/mci_boot_seqr.sv: Language not supported
- src/mci/rtl/mci_reg.rdl: Language not supported
- src/mci/rtl/mci_reg.sv: Language not supported
- src/mci/rtl/mci_reg_pkg.sv: Language not supported
- src/mci/rtl/mci_reg_top.sv: Language not supported
- src/mci/rtl/mci_reg_uvm.sv: Language not supported
- src/mci/rtl/mci_top.sv: Language not supported
- src/mci/rtl/mci_top_defines.svh: Language not supported
Automatic hash stamp failed due to a test header file that was modified locally as part of normal execution of L0 testsuite. Will be resolved in future PR.
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Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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…e/caliptra-ss into ckuchta-mci-reset-updates
…r mbox instance, add to L1 and nightly (#227) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * -Refactor MCU mbox tests to be able to select instance -Mbox0 in L0/Promote -Mbox1 added to L1 * -Update testname * -Revert to using BUILD_CFLAGS * -Add MCU mbox test to verify user locked out of mailbox between execute clear and zeroize finished * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * PR feedback * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes #177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * PR feedback * PR feedback. * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/keithjenkins/mbox_val_2' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: andrea-caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> Co-authored-by: Anjana Parthasarathy <107714838+anjpar@users.noreply.github.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com>
…ted timestamp and hash after successful run
…ted timestamp and hash after successful run
…e/caliptra-ss into ckuchta-mci-reset-updates
…e/caliptra-ss into ckuchta-mci-reset-updates
…iance/caliptra-ss into ckuchta-mci-reset-updates
* [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Add MCU SRAM byte write test with new MCI lib C files * Add smoke_test_mcu_sram_byte_write to regressions * Add MCU SRAM Protected Region test to regression Random test that does positive and negative testing on the MCU SRAM protected region. Some new C commands were needed to disable assertions in MCU SRAM when doing negative testing. A new soc_ifc_ss library was added for Caliptra Core C code to use. * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * Fix smoke_test_mcu_sram_protected_region Missing comment // in smoke_test_mcu_sram_protected_region.c Changed DMA error message to be DMA Err preventing regex test failure * Update src/integration/test_suites/libs/soc_ifc_ss/soc_ifc_ss.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fix typo protection -> pretected * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-test' with updated timestamp and hash after successful run * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * Fix MCI REG config locking * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes #177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * Fix C build issue * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Add general init fucntion mcu_cptra_init() This function should be used by the majority of C tests to: 1. Configure MCI registers 2. Bring Caliptra out of reset 3. Set Caliptra Fuses 4. Bring Caliptra Core out of reset * Fix type in smoke_test_mcu_mbox.c * Fix type on smoke_test_lcc_scrap.c * Add back mcu_cptra_user_init This is used to configure the SOC_IFC. Adding back to fix mcu_cptra_bringup test. * Update MCI memory map and Address with calculation (#228) * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * [VAL] Add MCU mbox user lockout test, refactor existing mbox tests for mbox instance, add to L1 and nightly (#227) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * -Refactor MCU mbox tests to be able to select instance -Mbox0 in L0/Promote -Mbox1 added to L1 * -Update testname * -Revert to using BUILD_CFLAGS * -Add MCU mbox test to verify user locked out of mailbox between execute clear and zeroize finished * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * PR feedback * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes #177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 # Conflicts: # src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * PR feedback * PR feedback. * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/keithjenkins/mbox_val_2' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: andrea-caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> Co-authored-by: Anjana Parthasarathy <107714838+anjpar@users.noreply.github.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Fix mcu_hello_world.c failure * Fix failed regressions * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-test' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> Co-authored-by: andrea-caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Co-authored-by: Anjana Parthasarathy <107714838+anjpar@users.noreply.github.com> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org>
Caliptra is the "mcu_sram_config_axi_user" not the "mci_config_axi_user" and we need Caliptra to update this register.
…e/caliptra-ss into ckuchta-mci-reset-updates
* fixed cov err and pre-hash err * integ lcc and fc rdl in soc addr map * removed a redun check * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/lcc_env_fix' with updated timestamp and hash after successful run * removed a hardcoded offset in axi_addr_assig
…e/caliptra-ss into ckuchta-mci-reset-updates
…updated timestamp and hash after successful run
…updated timestamp and hash after successful run
ekarabu
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Apr 7, 2025
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Apr 7, 2025
…pec (#235) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-01' with updated timestamp and hash after successful run * Add MCU hitless flows to spec and update RESET_REASON register We want the RESET_REASON register to be updated by Caliptra FW instead of all done in HW. This gives greater flexability to the design and will help with any corner cases we may encounter. * Manually re-stamp repo after pipeline passed. Automatic hash stamp failed due to a test header file that was modified locally as part of normal execution of L0 testsuite. Will be resolved in future PR. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fix typo in CaliptraSSIntegrationSpecification.md * [VAL] Add MCU mbox user lockout test, refactor existing mbox tests for mbox instance, add to L1 and nightly (#227) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * -Refactor MCU mbox tests to be able to select instance -Mbox0 in L0/Promote -Mbox1 added to L1 * -Update testname * -Revert to using BUILD_CFLAGS * -Add MCU mbox test to verify user locked out of mailbox between execute clear and zeroize finished * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * PR feedback * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * PR feedback * PR feedback. * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/keithjenkins/mbox_val_2' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: andrea-caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> Co-authored-by: Anjana Parthasarathy <107714838+anjpar@users.noreply.github.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [DOC] Fix regression file link in README (#236) * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-03' with updated timestamp and hash after successful run * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-03' with updated timestamp and hash after successful run * Add RESET_REASON write to test due to new HW * [VAL] Add MCU SRAM Byte Test and Prot Region Test (#223) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Add MCU SRAM byte write test with new MCI lib C files * Add smoke_test_mcu_sram_byte_write to regressions * Add MCU SRAM Protected Region test to regression Random test that does positive and negative testing on the MCU SRAM protected region. Some new C commands were needed to disable assertions in MCU SRAM when doing negative testing. A new soc_ifc_ss library was added for Caliptra Core C code to use. * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * Fix smoke_test_mcu_sram_protected_region Missing comment // in smoke_test_mcu_sram_protected_region.c Changed DMA error message to be DMA Err preventing regex test failure * Update src/integration/test_suites/libs/soc_ifc_ss/soc_ifc_ss.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fix typo protection -> pretected * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-test' with updated timestamp and hash after successful run * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * Fix MCI REG config locking * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * Fix C build issue * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM…
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) * enable mcu tap access basic register access test through jtag fix bug in address decode GH issue #199 * temp commit of jtag reg test collateral * re instantiated jtagdpi for caliptra core, both can work at the same time test updates for mcu jtag access to mcu sram * fix to dmi access to mcu sram dmi address and data registers were not actually hooked up to mcu sram connected the dmi write data to the sram address and perform a speculative read when writing the address register store the results in another register to be read when reading the data register address register is updated on writes to dmi mcu sram address reg, use this address when a write to the data register is detected along with the dmi write data on the sram wdata interface * rename jtag mcu test to jtag mcu unlock new jtag mcu test for debug intent * remove old jtag mcu test after rename * fix field ordering in agg error registers connect mcu system bus for jtag debug * add mcu bp test with jtag setting GO add finished debug intent jtag reg permissions test add tb services to set breakpoint fix locked debug dmi register read mux in mci reg top * add debug unlock flag to tb services for jtag testing fix broken fw for jtag mcu unlock case * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/ss_mcu_jtag' with updated timestamp and hash after successful run * [RTL][DOC] Update MCI RESET_RESON register and add HITLESS flows to spec (#235) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-01' with updated timestamp and hash after successful run * Add MCU hitless flows to spec and update RESET_REASON register We want the RESET_REASON register to be updated by Caliptra FW instead of all done in HW. This gives greater flexability to the design and will help with any corner cases we may encounter. * Manually re-stamp repo after pipeline passed. Automatic hash stamp failed due to a test header file that was modified locally as part of normal execution of L0 testsuite. Will be resolved in future PR. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fix typo in CaliptraSSIntegrationSpecification.md * [VAL] Add MCU mbox user lockout test, refactor existing mbox tests for mbox instance, add to L1 and nightly (#227) * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * -Refactor MCU mbox tests to be able to select instance -Mbox0 in L0/Promote -Mbox1 added to L1 * -Update testname * -Revert to using BUILD_CFLAGS * -Add MCU mbox test to verify user locked out of mailbox between execute clear and zeroize finished * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * PR feedback * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (DCCM, I-Cache) to dedicated VeeR export; move other logic to tb_services * Rename CSS CLK FREQ override var in Makefile * Verilog hierarchical names cleanup * Update file-list * Connect some NC signals - w_stub is out of date * Fix comment text for command encode * Move hier path defines to separate file * Additional syntax fixes for w_stub * More syntax fixes, header includes * Remove old defunct mcu coverage files * Add SHA accel test using Caliptra DMA Assist - Drive undriven signals in AXI interfaces: - Upper ADDR bits - AxCACHE, AxPROT, AxREGION, AxQOS - Avery assertions (enable AXI monitor) - Caliptra SS top coverage file - Drive MCI/CALIPTRA base addr strap inputs to SS top - Add new opcode in ss tb services to preload mcu_sram with SHA vector - Add test to run SHA accelerator from MCU SRAM via AXI * Clear SHA lock out of reset * Replace burst DMA txn with single-dw due to AXI interconnt dwidth conversion issue * Add mcu sram SHA accel test to nightly directed regression * Add some debug prints and change verbosity * Regenerate file-lists * avery monitor on flag * Add coverpoints for AXI DMA access to mcu_sram, mci regs, FC * Use params for soc_ifc addr config; add FIFO apertures for FIXED burst access * Remove commented code * Move mcu_sleep to header so all importers can use it * Add wait/timeouts on polling functions * truncate ending newline to eliminate git diff * Put MCU SRAM SHA test in Random, not directed regr * Move coverage bind files to tb_services --------- Co-authored-by: kedjenks <kedjenks@gmail.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Update MCI memory map and Address with calculation (#228) * PR feedback * PR feedback. * [TB] Halt MCU at end of tests to quiesce AXI i/f (#232) * Halt MCU before ending test so that AXI i/f quiesces * Halt MCU at end of testcase * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/keithjenkins/mbox_val_2' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: andrea-caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> Co-authored-by: Anjana Parthasarathy <107714838+anjpar@users.noreply.github.com> Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [DOC] Fix regression file link in README (#236) * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-03' with updated timestamp and hash after successful run * MICROSOFT AUTOMATED PIPELINE: Stamp 'msft-daily-2025-04-03' with updated timestamp and hash after successful run * Add RESET_REASON write to test due to new HW * [VAL] Add MCU SRAM Byte Test and Prot Region Test (#223) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Add MCU SRAM byte write test with new MCI lib C files * Add smoke_test_mcu_sram_byte_write to regressions * Add MCU SRAM Protected Region test to regression Random test that does positive and negative testing on the MCU SRAM protected region. Some new C commands were needed to disable assertions in MCU SRAM when doing negative testing. A new soc_ifc_ss library was added for Caliptra Core C code to use. * [fuse_ctrl, test] caliptra _ss _fuse_ctrl_unexpected_reset (#215) * [fuse_ctrl, mmap] Split debug unlock key fuses Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] caliptra_ss_fuse_ctrl_unexpected_reset Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, axi] Adapt AXI ranges to new MMAP Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * [fuse_ctrl, test] Use random seed in config files Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> * MICROSOFT AUTOMATED PIPELINE: Stamp 'lowrisc_caliptra_ss_fuse_ctrl_unexpected_reset' with updated timestamp and hash after successful run --------- Signed-off-by: Andrea Caforio <andrea.caforio@lowrisc.org> Co-authored-by: Andrea Caforio (LOWRISC C I C) <v-acaforio@microsoft.com> * Fix smoke_test_mcu_sram_protected_region Missing comment // in smoke_test_mcu_sram_protected_region.c Changed DMA error message to be DMA Err preventing regex test failure * Update src/integration/test_suites/libs/soc_ifc_ss/soc_ifc_ss.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> * Fix typo protection -> pretected * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-test' with updated timestamp and hash after successful run * Add random tests for Caliptra SS and update regression yaml generation script to generate nightly random regression yaml file. Update regression yaml files for new tests (#226) * Fix MCI REG config locking * [TB] Add LCC random tests (#225) * [fuse_ctrl, script] Move to common directory This commit moves the gen_fuse_ctrl_partitions scripts to a common fuse_ctrl_script directory such that the lib can be reused by other scripts. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Add VMEM generation script This commit adds a script that generated VMEM files that can be loaded into the fuse controller. The life cycle state, counter, and the transition token can be programed by using cmd line arguments. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, lib] Extend lc_ctrl library This commit adds functions to the lc_ctrl library that could be useful for different tests. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] LCC transition test This commit adds a simple LCC transition test. The test reads the current LCC state and tries to jump into the next one. By using the script tools/scripts/fuse_ctrl_script/design/gen_fuse_ctrl_vmem.py different starting LC states and unlock tokens can be tested. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Allow to configure multiple tokens This commit extends the VMEM generation script such that multiple tokens can be programmed into OTP vmem. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add README to caliptra_ss_lcc_st_trans This commit adds a README to guide the user to run the test. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Add smoke_test_lcc_kmac_kat As the KMAC core is inside the lc_ctrl and there is no direct access for SW, this test indirectly tests the KMAC output. - Step 1: gen_fuse_ctrl_vmem.py parses the unhashed token from test_unlock_token.hjson and writes them hashed into the otp-img.2048.vmem file - Step 2: smoke_test_kmac_kat.c contains the same unhashed tokens. The test performs state transitions from TEST_LOCKED0 to PROD_END. If the state transition was successful, the unhashed token was correctly hashed by the KMAC block and matches the hashed token that was generated by the SHAKE reference implementation in gen_fuse_ctrl_vmem.py Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [fuse_ctrl, script] Random parameter generation This commit extends the gen_fuse_ctrl_vmem script such that the unlock tokens, the LC counter, and LC state can be generated randomly. Moreover, a C header file can be generated that contains the unhased tokens that are programmed into VMEM. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomly generate unlock tokens This commit extends the test run script such that the gen_fuse_ctrl_vmem.py script is used to randomize the state transition unlock tokens. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Randomize caliptra_ss_lcc_st_trans This test randomizes the caliptra_ss_lcc_st_trans test by calling the gen_fuse_ctrl_vmem.py script that will put a random LC_STATE and LC_CNT into the otp vmem file. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Switch mode of tests - caliptra_ss_lcc_st_trans: Use random LC state & LC counter but fixed unlock tokens - smoke_test_lcc_kmac_kat: Use random unlock token but fixed starting LC state and LC counter Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,dv] Add covergroups for LC_CNT and LC_STATE This commit adds simple covergroups for the LC counter value and LC state. Bins are added to make sure that all possible states and counters have been seen. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, sw] Fix LC_CTRL STATUS INIT/READY mask LC_CTRL.STATUS.READY should be bit 1 in the bit field and LC_CTRL.STATUS.INIT should be bit 0 in the bit field. Closes chipsalliance/caliptra-ss#177 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * updated .vf file * [script] Add additional python requirements Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl,test] Use error function when expecting an error Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * [lc_ctrl, test] Use PB Random Seed To generate the randomized OTP VMEM image. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> * added vf files with new sim_tools --------- Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Pascal Nasahl <nasahlpa@lowrisc.org> * Fix C build issue * [TB] Add MCU_SRAM -> SHA Accel test case (using DMA assist) (#222) * [RTL, TB] Route MCU interrupts to top-level for override; cleanup testbench (#195) * Remove unused axi ifs, TB interrupt control logic, and ICCM components * Dummy tweak to axi2tlul compile * Whitespace * Fix a display about i3c wait time * Add comment to trigger file-list check * Restore axi2tlul compile.yml * Connect external interrupts for MCU to top-level for integrator override * Use central command list/params to define TB services behavior * Whitespace * Use central soc_address_map.h and remove duplicates * Generate caliptra_ss_clk_freq with default value for all tests so it doesn't cause compile failures * Rename clk freq variable * Revert test rename from merge conflict * [Val][RTL] Add MCU Mbox Tests and Fix Mbox1 Grant Bug (#200) * User/dev/ekarabulut/caliptra jtag manuf (#187) * added caliptra+mcu UDS c test * caliptra-rom is implemented with C test * updated uds based addr * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added manuf smoke test * updated uds_test for full fuse write * adjusted completion time of tcl * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * added header comments * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/caliptra_JTAG_manuf' with updated timestamp and hash after successful run * [RTL] Enable assertions for SS Integration TB (#158) * Enable assertions for SS Integration TB * Merge with TOT * Add missing driver for rst_mbox_lock_req There was a bad merge that didn't cause regressions to fail. Added back the missing logic * Add WUSER driver in LCC and FC We either need to verify these tieoffs of connect them to AXI interconnect * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run * Remove old assertions * Remove stale LIBS_MCI_DIR now in COMP_LIB_NAMES * Add back sb_axi_wvalid port connection to MCU Inadvertently removed this port in caliptra_ss_top.sv * Clean up AXI user connections at SS top Moved all user connections to a single location. Also, removed the MCU DMA AXI IF since it is unused in our design and reduce overhead of maintaining connections to MCU DMA that is unused plus having to add tieoffs to an interface that is unused. * Enable RUSER in axi interconnect * Add MCU hitless update hanshake to CSS HW spec and strap restrictions * Update MCI Boot FSM with MCU halt handshake states Halt handshake is needed to ensure MCU is halted and idle before reset is asserted. Otherwise there could be outstanding AXI transaction when MCU is reset by MCI. * Add halt/ack handshake between MCU and MCI * change "warm reset" to "cold reset" for MCI boot update We have a bug where FW_BOOT_UPD_RESET should be tracking the first update since cold reset, not warm reset. Updated the spec to match what HW should be doing. * Revert back cold reset to warm reset in MCI reset reason register I believe we should be tracking warm reset since Caliptra is reset on MCI warm reset and the FW_EXEC register is reset on warm reset. * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Update docs/CaliptraSSHardwareSpecification.md Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> * Fix grammar per PR review * Clarify hitless update types * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Remove OtpKeymgrKeyKnown_A assertion since otp_broadcast_o doesn't exist * Fix Caliptra SS assertions Include caliptra_ss_assertion_overrides.svh in caliptra_ss_top_tb.sv. I think it was removed with a merge. Disable additional assertsions showing up in a TB Fuse module with a FIXME to remove and tagged with a github issue. * Fix decode issue where MBOX1 was granted when MBOX0 targeted * Fix build issue, duplicate assertion names * MICROSOFT AUTOMATED PIPELINE: Stamp 'ckuchta-mcu-sram-val' with updated timestamp and hash after successful run --------- Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * Add new test for I3C and Streaming boot (#161) * Initial test code for bringup with local caliptra-core images * Ending quote - syntax * Reorganize ai3c tests * Rename ai3ct test as svh, since it's an include * Add a top-level include file that grabs all css ai3c tests * Remove recipe for program.hex * Add caliptra subsystem macro to compile.yml; update test-suites with plusargs/pre_exec * Fix user signals and config so design boots with Caliptra ROM * Use DEBUG_OUT as STDOUT in ss sims * Regenerate RDL files and update workflow to catch out of date RDL * Unique AxUSER for Caliptra, MCU-LSU, and MCU-IFU * Fixes to get cptra_ss_i3c_recovery pre-exec working * Initialize data/bss/STACK to DCCM, as the MCU SRAM is locked at startup * Remove cptra AxUSER force; TMP: set cptra AxUSER as SOC CONFIG user * Update RTL submodule to pull fw_test_rom updates * Add explanatory note/TODO on LSU user * Revert changes to mcu_hello_world -- it's a defunct test * Makefile cleanup * Rename top test list file * Reorganize the libs area * Move mcu bringup tasks to shared lib file; update Makefile to init data to DCCM and build libs * Roll back the USER/linker modifications to isolate just the methodology changes * Update testfile yml for all smoke tests * Whitespace * Hello world testcase that shows caliptra-core fw built from caliptra-ss repo * Don't build caliptra_isr for MCU - that's a caliptra-core file * Revert USER changes in i3c test * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-local-testcode-PoC' with updated timestamp and hash after successful run * I3C reg rd wr and caliptra streaming boot test rom * Removed the global switch * resolved conflicts. * Resolved conflicts. * Reg read write test updated to read and or write all the reg * Added Streaming boot random test * Added updates for Random and reg read write test * Cleanup commit * Removed Debug log * Updated for randomized block size * Add MCU MBOX Tests and Fix MBOX Lock Clearing Detection (#181) * -Fix mailbox release detection to be based on valid SW write and data being 0 (instead of value edge detect). -Update MBOX clearing to explicitly call out writing 0 to EXECUTE register. * -Add MCU MBOX smoke test with MCU and Caliptra both acquiring and reading/writing MBOX. -Add MCU MBOX lock return one during zeroize test. -Update MCU MBOX zeroize smoke test for new infra. -Add MCU MBOX tests to L0. * -Add MBOX CSRs are zero after lock release test. -Fix mbox_status CSR to reset on MBOX lock release. * Added support for Caliptra Test build in Makefile vcs * Disabled internal scoreboard for VIP --------- Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: kedjenks <kedjenks@gmail.com> * -Add MCU Mbox Valid User Smoke Test -Add MCU Mbox Write During User Lock Smoke Test -RTL Bug Fix for Incorrect Mbox1 grant connection. * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * Merge branch 'msft-daily-2025-03-28' of ssh://github.com/chipsalliance/caliptra-ss into user/dev/keithjenkins/mbox_val_1 * [DOCS] Update README with simulation instructions, env vars (#184) * Replace instances of the deprecated var CALIPTRA_SS with CALIPTRA_SS_ROOT (removes duplicate variables) * Remove duplicate macros * Document sim-flow, env var setup, and AXI4PC requirement * Formatting updates regarding note on AXI4PC * Clarification on axi4pc version * Fix a grammar error * Apply suggested updates to text about acquiring Axi4PC Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Run RDL check for all PRs, not just to main * Document that some CALIPTRA_TESTNAME code may be in its own directory in caliptra-ss * Regenerate reg map --------- Co-authored-by: Steven Bellock <sbellock@nvidia.com> * Rename test * Rename. * -Refactor MCU mbox test code to move some functions to ss_lib -Address PR comment feedback * Address stride fix for AXI CFG registers * PR feedback: -Remove unneeded soc_address_map.h * Fix bad merge conflict * Address PR feedback -Move CMD_Available interrupt to wait for execute function -Add RW1C interrupt clear and checking --------- Co-authored-by: EMRE KARABULUT <63821295+ekarabu@users.noreply.github.com> Co-authored-by: clayton8 <ckuchta@microsoft.com> Co-authored-by: Caleb <11879229+calebofearth@users.noreply.github.com> Co-authored-by: Nilesh Patel <142342517+nileshbpat@users.noreply.github.com> Co-authored-by: Caleb Whitehead <cwhitehead@microsoft.com> Co-authored-by: Steven Bellock <sbellock@nvidia.com> * [TB] Reorganize testbench code into services and mem export files (#206) * Move MCU SRAM (D…
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