[RDL, TB] Make MCI debug regs 32-bit; fix MCU SRAM exec testcase

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-b62349132bcf80e95c2a701397c1f37a288cf5f4aa9b3ae5e67ed23f629973ef9bb6c295bc5426df30264b81200a181a
+8581e74025a880b4fb1fc72f409a923ea51eab958d362f5ac12a5d8cddd78e17668286cbe44537a06bc491dc89ca6c09

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1744070256
+1744086464

src/integration/coverage/caliptra_ss_top_cov_if.sv

@@ -57,23 +57,23 @@ interface caliptra_ss_top_cov_if
             bins b2b_axi_txn = (1 [*5]); //5 txns in a row
         }
 
-        axi_rd_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
+        axi_rd_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.araddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
             bins axi_rd_req = {1'b1};
         }
-        axi_wr_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
+        axi_wr_mci_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awaddr inside {[`SOC_MCI_TOP_BASE_ADDR:`SOC_MCI_TOP_MCU_TRACE_BUFFER_CSR_BASE_ADDR-4]} {
             bins axi_wr_req = {1'b1};
         }
-        axi_rd_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
+        axi_rd_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.araddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
             bins axi_rd_req = {1'b1};
         }
-        axi_wr_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
+        axi_wr_mcu_sram: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awaddr inside {[`SOC_MCI_TOP_MCU_SRAM_BASE_ADDR:`SOC_MCI_TOP_MCU_SRAM_END_ADDR]} {
             bins axi_wr_req = {1'b1};
         }
         // FIXME replace these magic numbers with some macro once soc_address_map is updated
-        axi_rd_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.arraddr inside {[64'h7000_0000:64'h7000_03FF]} {
+        axi_rd_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_ar_hshake && cptra_ss_cptra_core_m_axi_if.araddr inside {[64'h7000_0000:64'h7000_03FF]} {
             bins axi_rd_req = {1'b1};
         }
-        axi_wr_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awraddr inside {[64'h7000_0000:64'h7000_03FF]} {
+        axi_wr_fc_regs: coverpoint cptra_ss_cptra_core_m_axi_if_aw_hshake && cptra_ss_cptra_core_m_axi_if.awaddr inside {[64'h7000_0000:64'h7000_03FF]} {
             bins axi_wr_req = {1'b1};
         }
     endgroup

src/integration/rtl/soc_address_map.h

@@ -7237,14 +7237,10 @@
 #define SOC_MCI_TOP_MCI_REG_DEBUG_IN                                                                (0x21000410)
 #ifndef MCI_REG_DEBUG_IN
 #define MCI_REG_DEBUG_IN                                                                            (0x410)
-#define MCI_REG_DEBUG_IN_DATA_LOW                                                                   (0)
-#define MCI_REG_DEBUG_IN_DATA_MASK                                                                  (0x1)
 #endif
 #define SOC_MCI_TOP_MCI_REG_DEBUG_OUT                                                               (0x21000414)
 #ifndef MCI_REG_DEBUG_OUT
 #define MCI_REG_DEBUG_OUT                                                                           (0x414)
-#define MCI_REG_DEBUG_OUT_DATA_LOW                                                                  (0)
-#define MCI_REG_DEBUG_OUT_DATA_MASK                                                                 (0x1)
 #endif
 #define SOC_MCI_TOP_MCI_REG_SS_DEBUG_INTENT                                                         (0x21000418)
 #ifndef MCI_REG_SS_DEBUG_INTENT

src/integration/rtl/soc_address_map_field_defines.svh

@@ -6756,13 +6756,9 @@
 `endif
 `ifndef MCI_REG_DEBUG_IN
 `define MCI_REG_DEBUG_IN                                                                            (32'h410)
-`define MCI_REG_DEBUG_IN_DATA_LOW                                                                   (0)
-`define MCI_REG_DEBUG_IN_DATA_MASK                                                                  (32'h1)
 `endif
 `ifndef MCI_REG_DEBUG_OUT
 `define MCI_REG_DEBUG_OUT                                                                           (32'h414)
-`define MCI_REG_DEBUG_OUT_DATA_LOW                                                                  (0)
-`define MCI_REG_DEBUG_OUT_DATA_MASK                                                                 (32'h1)
 `endif
 `ifndef MCI_REG_SS_DEBUG_INTENT
 `define MCI_REG_SS_DEBUG_INTENT                                                                     (32'h418)

src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml

@@ -12,6 +12,7 @@ contents:
         - ../test_suites/smoke_test_fc_random_item_prov/smoke_test_fc_random_item_prov.yml
         - ../test_suites/smoke_test_fc_registers/smoke_test_fc_registers.yml
         - ../test_suites/mcu_hello_world/mcu_hello_world.yml
+        - ../test_suites/mcu_lmem_exe/mcu_lmem_exe.yml
         - ../test_suites/smoke_test_lcc_scrap/smoke_test_lcc_scrap.yml
         - ../test_suites/smoke_test_lcc_RMA/smoke_test_lcc_RMA.yml
         - ../test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov.yml

src/integration/stimulus/L1_Nightly_Directed_caliptra_ss_top_tb_regression.yml

@@ -14,7 +14,7 @@ contents:
         $CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_cptra_bringup/mcu_cptra_bringup: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/cptra_ss_i3c_recovery/cptra_ss_i3c_recovery: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/i3c_smoke/i3c_smoke: { weight: 100 }
-        $CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_dccm_access/mcu_dccm_access: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_hello_world/mcu_hello_world: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_lmem_exe/mcu_lmem_exe: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_scrap/smoke_test_lcc_scrap: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov: { weight: 100 }

src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv

@@ -7,9 +7,8 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_fc_random_item_prov/smo
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_fc_registers/smoke_test_fc_registers                                           , None           , None          , L0  , None, caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/cptra_ss_i3c_recovery/cptra_ss_i3c_recovery                                               , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/i3c_smoke/i3c_smoke                                                                       , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
-$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_dccm_access/mcu_dccm_access                                                           , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
-$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_hello_world/mcu_hello_world                                                           , None           , None          , L0  , None, caliptra_ss_top_tb, Promote        , None     , 100
-$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_lmem_exe/mcu_lmem_exe                                                                 , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_hello_world/mcu_hello_world                                                           , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/mcu_lmem_exe/mcu_lmem_exe                                                                 , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_scrap/smoke_test_lcc_scrap                                                 , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_RMA/smoke_test_lcc_RMA                                                     , Random         , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_manuf_prod_prov/caliptra_ss_fuse_ctrl_manuf_prod_prov               , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100

src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h

@@ -69,10 +69,27 @@ typedef struct {
     bool cfg_skip_set_fuse_done;
 
 } mcu_cptra_init_args;
+#define mcu_cptra_init_arg_defaults           \
+    /* FW_SRAM_EXEC_REGION_SIZE */            \
+    .cfg_mcu_fw_sram_exec_reg_size   = false, \
+    .mcu_fw_sram_exec_reg_size       = 0,     \
+    /* CPTRA DMA AXI USER */                  \
+    .cfg_cptra_dma_axi_user          = false, \
+    .cptra_dma_axi_user              = 0,     \
+    /* MCU MBOX VALID USER */                 \
+    .cfg_mcu_mbox0_valid_user        = false, \
+    .mcu_mbox0_valid_user            = 0,     \
+    .cfg_mcu_mbox1_valid_user        = false, \
+    .mcu_mbox1_valid_user            = 0,     \
+    /* SOC_IFC MBOX */                        \
+    .cfg_enable_cptra_mbox_user_init = false, \
+    /* FUSE DONE */                           \
+    .cfg_skip_set_fuse_done          = false
+
 // MAIN CPTRA INIT FUNCTION EVERYONE SHOULD USER 
 // TO LOAD FUSES!!!
 void mcu_cptra_init(mcu_cptra_init_args args);
-#define mcu_cptra_init_d(...) mcu_cptra_init((mcu_cptra_init_args){__VA_ARGS__});
+#define mcu_cptra_init_d(...) mcu_cptra_init((mcu_cptra_init_args){mcu_cptra_init_arg_defaults __VA_OPT__(,) __VA_ARGS__});
 
 uint32_t xorshift32(void);
 
@@ -81,7 +98,7 @@ extern uint32_t valid_mbox_instances;
 uint32_t decode_single_valid_mbox(void);
 
 inline void mcu_sleep (const uint32_t cycles) {
-    for (uint8_t ii = 0; ii < cycles; ii++) {
+    for (uint32_t ii = 0; ii < cycles; ii++) {
         __asm__ volatile ("nop"); // Sleep loop as "nop"
     }
 }

src/integration/test_suites/libs/riscv_hw_if/link.ld

@@ -23,17 +23,26 @@ SECTIONS {
   . = 0x50000000;
   .dccm : { *(.dccm) }
   _dccm_end = .;
-  .data : { *(.*data) *(.rodata*) *(.srodata*) }
+  .data : { *(.data) *(.data.*) *(.sdata) *(.sdata.*) ; . = ALIGN(4); } =0x0000,
   _data_end = .;
-  .bss : { *(.bss) *(.sbss) }
+  .bss : { *(.bss) *(.sbss) ; . = ALIGN(4); } =0x0000,
   _bss_end = .;
 
   STACK = ALIGN(16) + 0x1000;
+  ASSERT( STACK < 0x50004000, "ERROR: STACK allocation exceeds DCCM size of 16KiB")
 
   . = 0x80000000;
-  .text   : { *(.text*) }
+  .text   : { *(.text*) ; . = ALIGN(4); } =0x0000,
   _text_end = .;
+  .rodata : { *(.rodata*) *(.srodata*) ; . = ALIGN(4); } =0x0000,
+  _rodata_end = .;
+  ASSERT( _rodata_end < 0x80040000, "ERROR: ROM size exceeds 256KiB")
 
   . = 0x21000414;
   .data.io : { *(.data.io) }
-}
+
+  . = 0x21C00000;
+  .mcu_sram : { *(.mcu_sram*) ; . = ALIGN(4); } =0x0000,
+  _mcu_sram_end = .;
+  ASSERT( _mcu_sram_end < 0x21C7FFFF, "ERROR: MCU SRAM size exceeds 512KiB")
+}

src/integration/test_suites/libs/caliptra_isr/veer-csr.h → src/integration/test_suites/libs/riscv_hw_if/veer-csr.h

@@ -23,10 +23,12 @@
 //////////////////////////////////////////////////////////////////////////////
 // Non-Standard VeeR CSR offset macros
 //
+#define VEER_CSR_MPMC     0x7C6
 #define VEER_CSR_MICECT   0x7F0
 #define VEER_CSR_MICCMECT 0x7F1
 #define VEER_CSR_MDCCMECT 0x7F2
 #define VEER_CSR_MSCAUSE  0x7FF
+#define VEER_CSR_MDEAU    0xBC0
 #define VEER_CSR_MEIVT    0xBC8
 #define VEER_CSR_MEIPT    0xBC9
 #define VEER_CSR_MEICPCT  0xBCA
@@ -88,26 +90,44 @@ enum {
 #define MCAUSE_NMI_CODE_FAST_INT_DCCM_VALUE     (MCAUSE_NMI_BIT_MASK | 0x1001)
 #define MCAUSE_NMI_CODE_FAST_INT_NONDCCM_VALUE  (MCAUSE_NMI_BIT_MASK | 0x1002)
 
+/*******************************************
+ * mpmc - MRW - Power Management Control Register
+ */
+static inline void csr_write_mpmc(uint_xlen_t value) {
+    __asm__ volatile ("csrw    %0, %1" \
+                : /* output: none */        \
+                : "i" (VEER_CSR_MPMC), "r" (value)  /* input : immediate  */ \
+                : /* clobbers: none */);
+}
+static inline void csr_write_mpmc_halt() {
+    //Halt the core
+    __asm__ volatile ("csrwi    %0, %1" \
+                : /* output: none */        \
+                : "i" (VEER_CSR_MPMC), "i" (0x03)  /* input : immediate  */ \
+                : /* clobbers: none */);
+}
+
+
 /*******************************************
  * mdeau - MRW - Data base register.
  */
 static inline uint_xlen_t csr_read_mdeau(void) {
     uint_xlen_t value;
-    __asm__ volatile ("csrr    %0, 0xbc0"
+    __asm__ volatile ("csrr    %0, VEER_CSR_MDEAU"
                       : "=r" (value)  /* output : register */
                       : /* input : none */
                       : /* clobbers: none */);
     return value;
 }
 static inline void csr_write_mdeau(uint_xlen_t value) {
-    __asm__ volatile ("csrw    0xbc0, %0"
+    __asm__ volatile ("csrw    VEER_CSR_MDEAU, %0"
                       : /* output: none */
                       : "r" (value) /* input : from register */
                       : /* clobbers: none */);
 }
 static inline uint_xlen_t csr_read_write_mdeau(uint_xlen_t new_value) {
     uint_xlen_t prev_value;
-    __asm__ volatile ("csrrw    %0, 0xbc0, %1"
+    __asm__ volatile ("csrrw    %0, VEER_CSR_MDEAU, %1"
                       : "=r" (prev_value) /* output: register %0 */
                       : "r" (new_value)  /* input : register */
                       : /* clobbers: none */);

src/integration/test_suites/mcu_cptra_bringup/mcu_cptra_bringup.c

@@ -101,24 +101,5 @@ void main (void) {
         mcu_mci_req_reset();
         while(1);
     }
-    // lsu_write_32(0x21200000, 0x12345678);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_0000 write completed\n");
-    // lsu_write_32(0x21200004, 0xABCDABCD);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_0004 write completed\n");
-    // lsu_write_32(0x21203FFC, 0xDEADDEAD);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_03FC write completed\n");
-
-    // mbox_resp_data = lsu_read_32(0x21200000);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_0000 %x\n", mbox_resp_data);
-    // mbox_resp_data = lsu_read_32(0x21200004);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_0004 %x\n", mbox_resp_data);
-    // mbox_resp_data = lsu_read_32(0x21203FFC);
-    // VPRINTF(LOW, "MCU: I3C 0x2120_03FC %x\n", mbox_resp_data);
-
-    // mbox_resp_dlen = lsu_read_32(I3CCSR_I3CBASE_CONTROLLER_DEVICE_ADDR);
-    // VPRINTF(LOW, "MCU: I3C I3CCSR_I3CBASE_CONTROLLER_DEVICE_ADDR %x\n", mbox_resp_dlen);
-
-    // lsu_write_32(SOC_I3CCSR_I3CBASE_HC_CONTROL, 0x12345678);
-    // VPRINTF(LOW, "MCU: I3C SOC_I3CCSR_I3CBASE_HC_CONTROL write completed\n");
 
 }

src/integration/test_suites/mcu_hello_world/mcu_hello_world.c

@@ -31,17 +31,23 @@ volatile char* stdout = (char *)SOC_MCI_TOP_MCI_REG_DEBUG_OUT;
     enum printf_verbosity verbosity_g = LOW;
 #endif
 
+// Global variable allocated to DCCM explicitly, to test DCCM access
+static const char* dccm_msg __attribute__ ((section(".dccm"))) = "=================\nHello World from MCU DCCM\n=================\n\n";
+
 void main (void) {
     int argc=0;
     char *argv[1];
     uint32_t reg_data;
 
-    VPRINTF(LOW, "=================\nMCU: Subsytem Bringup Test\n=================\n\n")
+    // Print message from DCCM memory
+    if (dccm_msg[0] != '=') {
+        VPRINTF(FATAL, "MCU: DCCM does not contain expected message!\nExpected: '=', saw '%c'\n", dccm_msg[0]);
+    } else {
+        VPRINTF(LOW, dccm_msg)
+    }
 
     VPRINTF(LOW, "MCU: Caliptra bringup\n")
     mcu_cptra_init_d();
 
     mcu_cptra_poll_mb_ready();
-
-    SEND_STDOUT_CTRL(0xff);
 }