[VAL][RTL] MCU MBOX ECC Test and Update HW_STATUS to clear on lock

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-78f6efc752fcd38a3745c97b0cef8d106eb96d4f9c974eae8fe600c2a606962814d8a0f0ab5f3f6a47a33f5e5766a616
+64493d2343dc772a4b45093173182d340aff16da171a0f3ee8cb4ef6d7c802ad6be15409444c707f2345b11063eaa624

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1744315495
+1744401255

src/integration/stimulus/L0_Promote_caliptra_ss_top_tb_regression.yml

@@ -35,6 +35,7 @@ contents:
         - ../test_suites/smoke_test_mcu_mbox_usr_lock_out_zero/smoke_test_mcu_mbox0_usr_lock_out_zero.yml
         - ../test_suites/smoke_test_mcu_mbox_target_user/smoke_test_mcu_mbox0_target_user.yml
         - ../test_suites/smoke_test_mcu_mbox_invalid_axi/smoke_test_mcu_mbox0_invalid_axi.yml
+        - ../test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox0_ecc.yml
         - ../test_suites/smoke_test_lcc_kmac_kat/smoke_test_lcc_kmac_kat.yml
         - ../test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans.yml
         - ../test_suites/caliptra_ss_fuse_ctrl_external_clock/caliptra_ss_fuse_ctrl_external_clock.yml

src/integration/stimulus/L1_Nightly_Directed_caliptra_ss_top_tb_regression.yml

@@ -6,7 +6,7 @@ contents:
       tags: ["L1", "caliptra_ss_top_tb", "Directed", "Nightly"]
       path: ""
       weight: 100
-      generations: 360
+      generations: 380
       formats:
         generate: "reseed {template}.yml -seed {seed}"
         path: "{template_basename}__{seed}.yml"
@@ -42,6 +42,8 @@ contents:
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_target_user/smoke_test_mcu_mbox1_target_user: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_invalid_axi/smoke_test_mcu_mbox0_invalid_axi: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_invalid_axi/smoke_test_mcu_mbox1_invalid_axi: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox0_ecc: { weight: 100 }
+        $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox1_ecc: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_kmac_kat/smoke_test_lcc_kmac_kat: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans: { weight: 100 }
         $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_fuse_ctrl_integrity_check/caliptra_ss_fuse_ctrl_integrity_check: { weight: 100 }

src/integration/stimulus/testsuites/caliptra_ss_master_test_list.csv

@@ -42,6 +42,8 @@ $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_target_user/sm
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_target_user/smoke_test_mcu_mbox1_target_user                          , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_invalid_axi/smoke_test_mcu_mbox0_invalid_axi                          , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_invalid_axi/smoke_test_mcu_mbox1_invalid_axi                          , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox0_ecc                                          , Directed       , Nightly       , L0  , L1  , caliptra_ss_top_tb, Promote        , None     , 100
+$CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox1_ecc                                          , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/smoke_test_lcc_kmac_kat/smoke_test_lcc_kmac_kat                                           , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_lcc_st_trans/caliptra_ss_lcc_st_trans                                         , Directed       , Nightly       , None, L1  , caliptra_ss_top_tb, Promote        , None     , 100
 $CALIPTRA_SS_ROOT/src/integration/test_suites/caliptra_ss_mcu_sram_to_sha/caliptra_ss_mcu_sram_to_sha                                   , Random         , Nightly       , None, L1  , caliptra_ss_top_tb, None           , None     , 100

src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.c

@@ -352,6 +352,56 @@ bool is_mcu_mbox_clear_soc_req_while_mcu_lock_interrupt_set(uint32_t mbox_num) {
     return false;
 }
 
+bool is_only_mcu_mbox_sb_ecc_interrupt_set(uint32_t mbox_num) {
+    // Check that Mailbox SB ECC interrupt has been set
+    if(lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R) ==
+        (MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_ECC_COR_STS_MASK << mbox_num)) {
+            VPRINTF(LOW, "MCU: Mbox%x SB ECC interrupt set\n", mbox_num);
+            return true;
+    }
+    return false;
+}
+
+bool is_only_mcu_mbox_db_ecc_interrupt_set(uint32_t mbox_num) {
+    // Check that Mailbox DB ECC interrupt has been set
+    if(lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R) == 
+        (MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R_ERROR_MBOX0_ECC_UNC_STS_MASK << mbox_num)) {
+            VPRINTF(LOW, "MCU: Mbox%x DB ECC interrupt set\n", mbox_num);
+            return true;
+    }
+    return false;
+}
+
+void clear_mcu_mbox_clear_sb_ecc_interrupt(uint32_t mbox_num) {
+    VPRINTF(LOW, "MCU: RW1C SB ECC interrupt Mbox%x\n", mbox_num);
+    uint32_t internal_intr = lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R);
+    internal_intr = MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_ECC_COR_STS_MASK << mbox_num;
+    lsu_write_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R, internal_intr);
+
+    // Check that Mailbox SB ECC interrupt has been cleared
+    if((lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R) & 
+        (MCI_REG_INTR_BLOCK_RF_NOTIF0_INTERNAL_INTR_R_NOTIF_MBOX0_ECC_COR_STS_MASK << mbox_num)) != 0) {
+            VPRINTF(FATAL, "MCU: Mbox%x SB ECC interrupt not cleared\n", mbox_num);
+            SEND_STDOUT_CTRL(0x1);
+            while(1);
+    }
+}
+
+void clear_mcu_mbox_clear_db_ecc_interrupt(uint32_t mbox_num) {
+    VPRINTF(LOW, "MCU: RW1C DB ECC interrupt Mbox%x\n", mbox_num);
+    uint32_t internal_intr = lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R);
+    internal_intr = MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R_ERROR_MBOX0_ECC_UNC_STS_MASK << mbox_num;
+    lsu_write_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R, internal_intr);
+
+    // Check that Mailbox DB ECC interrupt has been cleared
+    if((lsu_read_32(SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R) & 
+        (MCI_REG_INTR_BLOCK_RF_ERROR0_INTERNAL_INTR_R_ERROR_MBOX0_ECC_UNC_STS_MASK << mbox_num)) != 0) {
+            VPRINTF(FATAL, "MCU: Mbox%x DB ECC interrupt not cleared\n", mbox_num);
+            SEND_STDOUT_CTRL(0x1);
+            while(1);
+    }
+}
+
 void mcu_mbox_configure_valid_axi(uint32_t mbox_num, uint32_t *axi_user_id) {
 
     VPRINTF(LOW, "MCU: Configuring Valid AXI USERs in Mbox%x:  0 - 0x%x; 1 - 0x%x; 2 - 0x%x; 3 - 0x%x; 4 - 0x%x;\n", mbox_num, axi_user_id[0], axi_user_id[1], axi_user_id[2], axi_user_id[3], axi_user_id[4]);

src/integration/test_suites/libs/caliptra_ss_lib/caliptra_ss_lib.h

@@ -48,6 +48,11 @@
 #define TB_CMD_DISABLE_INJECT_ECC_ERROR     0xe0
 #define TB_CMD_INJECT_ECC_ERROR_SINGLE_DCCM 0xe2
 #define TB_CMD_INJECT_ECC_ERROR_DOUBLE_DCCM 0xe3
+#define TB_CMD_INJECT_MBOX_SRAM_SINGLE_ECC_ERROR  0xe4
+#define TB_CMD_INJECT_MBOX_SRAM_DOUBLE_ECC_ERROR  0xe5
+#define TB_CMD_DISABLE_MBOX_SRAM_ECC_ERROR_INJECTION 0xe6
+#define TB_CMD_RANDOMIZE_MBOX_SRAM_ECC_ERROR_INJECTION 0xe7
+
 
 
 #define TB_CMD_COLD_RESET 0xF5
@@ -168,96 +173,101 @@ bool is_mcu_mbox_target_done_interrupt_set(uint32_t mbox_num);
 void mcu_mbox_clear_target_done_interrupt(uint32_t mbox_num);
 uint32_t mcu_mbox_get_sram_size_kb(uint32_t mbox_num);
 uint32_t mcu_mbox_gen_rand_dword_addr(uint32_t mbox_num, uint32_t sram_size_kb, uint32_t max_size_kb);
+bool is_only_mcu_mbox_sb_ecc_interrupt_set(uint32_t mbox_num);
+void clear_mcu_mbox_clear_sb_ecc_interrupt(uint32_t mbox_num);
+bool is_only_mcu_mbox_db_ecc_interrupt_set(uint32_t mbox_num);
+void clear_mcu_mbox_clear_db_ecc_interrupt(uint32_t mbox_num);
+
 
 ///////////////////////////////////////////////////
 // MCU Mbox Read/Write SRAM and CSR functions
 ////////////////////////////////////////////////////
-inline void mcu_mbox_clear_execute(uint32_t mbox_num) {
+static inline void mcu_mbox_clear_execute(uint32_t mbox_num) {
     VPRINTF(LOW, "MCU: Clearing MBOX%x Execute\n", mbox_num);
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_EXECUTE + MCU_MBOX_NUM_STRIDE * mbox_num, 0x0);
 }
 
-inline void mcu_mbox_set_execute(uint32_t mbox_num) {
+static inline void mcu_mbox_set_execute(uint32_t mbox_num) {
     VPRINTF(LOW, "MCU: Setting MBOX%x Execute\n", mbox_num);
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_EXECUTE + MCU_MBOX_NUM_STRIDE * mbox_num, 0x1);
 }
 
-inline void mcu_mbox_write_cmd(uint32_t mbox_num, uint32_t cmd) {
+static inline void mcu_mbox_write_cmd(uint32_t mbox_num, uint32_t cmd) {
     VPRINTF(LOW, "MCU: Writing to MBOX%x command: 0%x\n", mbox_num, cmd); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD + MCU_MBOX_NUM_STRIDE * mbox_num, cmd);
 }
-inline uint32_t mcu_mbox_read_cmd(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_cmd(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading CMD: 0x%x\n", mbox_num, rd_data); 
     return rd_data;
 }
-inline void mcu_mbox_write_dlen(uint32_t mbox_num, uint32_t dlen) {
+static inline void mcu_mbox_write_dlen(uint32_t mbox_num, uint32_t dlen) {
     VPRINTF(LOW, "MCU: Writing to MBOX%x DLEN: 0x%x\n", mbox_num, dlen); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_DLEN + MCU_MBOX_NUM_STRIDE * mbox_num, dlen);
 }
 
-inline uint32_t mcu_mbox_read_dlen(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_dlen(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_DLEN + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading DLEN: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
-inline void mcu_mbox_write_cmd_status(uint32_t mbox_num, enum mcu_mbox_cmd_status cmd_status) {
+static inline void mcu_mbox_write_cmd_status(uint32_t mbox_num, enum mcu_mbox_cmd_status cmd_status) {
     VPRINTF(LOW, "MCU: Writing to MBOX%x CMD_STATUS: 0%x\n", mbox_num, cmd_status); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD_STATUS + MCU_MBOX_NUM_STRIDE * mbox_num, (cmd_status & MCU_MBOX0_CSR_MBOX_CMD_STATUS_STATUS_MASK));    
 }
 
-inline uint32_t mcu_mbox_read_cmd_status(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_cmd_status(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_CMD_STATUS + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading CMD_STATUS: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
 
-inline uint32_t mcu_mbox_read_mbox_user(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_mbox_user(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_USER + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading USER: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
 
-inline uint32_t mcu_mbox_read_lock(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_lock(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_LOCK + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading LOCK: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
 
-inline uint32_t mcu_mbox_read_hw_status(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_hw_status(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_HW_STATUS + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading HW_STATUS: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
 
-inline void mcu_mbox_write_sram_dword(uint32_t mbox_num, uint32_t dword_addr, uint32_t data) {
-    VPRINTF(LOW, "MCU: Writing to MBOX%x data: 0x%x\n", mbox_num, data); 
+static inline void mcu_mbox_write_sram_dword(uint32_t mbox_num, uint32_t dword_addr, uint32_t data) {
+    VPRINTF(LOW, "MCU: Writing to MBOX%x SRAM[%d]: 0x%x\n", mbox_num, dword_addr, data); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_SRAM_BASE_ADDR + 4*dword_addr + MCU_MBOX_NUM_STRIDE * mbox_num, data);
 }
 
-inline uint32_t mcu_mbox_read_sram_dword(uint32_t mbox_num, uint32_t dword_addr) {
+static inline uint32_t mcu_mbox_read_sram_dword(uint32_t mbox_num, uint32_t dword_addr) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_SRAM_BASE_ADDR + 4*dword_addr + MCU_MBOX_NUM_STRIDE * mbox_num);
-    VPRINTF(LOW, "MCU: Mbox%x Reading SRAM: 0x%x\n", mbox_num, rd_data);
+    VPRINTF(LOW, "MCU: Mbox%x Reading SRAM[%d]: 0x%x\n", mbox_num, dword_addr, rd_data);
     return rd_data;
 }
 
-inline void mcu_mbox_write_target_user(uint32_t mbox_num, uint32_t axi_id) {
+static inline void mcu_mbox_write_target_user(uint32_t mbox_num, uint32_t axi_id) {
     VPRINTF(LOW, "MCU: Writing to MBOX%x TARGET_USER: 0%x\n", mbox_num, axi_id); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_TARGET_USER + MCU_MBOX_NUM_STRIDE * mbox_num, axi_id);    
 }
 
-inline uint32_t mcu_mbox_read_target_user(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_target_user(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_TARGET_USER + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading TARGET_USER: 0x%x\n", mbox_num, rd_data);
     return rd_data;
 }
 
-inline void mcu_mbox_write_target_user_valid(uint32_t mbox_num, uint32_t data) {
+static inline void mcu_mbox_write_target_user_valid(uint32_t mbox_num, uint32_t data) {
     VPRINTF(LOW, "MCU: Writing to MBOX%x TARGET_USER_VALID: 0x%x\n", mbox_num, data); 
     lsu_write_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_TARGET_USER_VALID + MCU_MBOX_NUM_STRIDE * mbox_num, (data & MCU_MBOX0_CSR_MBOX_TARGET_USER_VALID_VALID_MASK));    
 }
 
-inline uint32_t mcu_mbox_read_target_user_valid(uint32_t mbox_num) {
+static inline uint32_t mcu_mbox_read_target_user_valid(uint32_t mbox_num) {
     uint32_t rd_data = lsu_read_32(SOC_MCI_TOP_MCU_MBOX0_CSR_MBOX_TARGET_USER_VALID + MCU_MBOX_NUM_STRIDE * mbox_num);
     VPRINTF(LOW, "MCU: Mbox%x Reading TARGET_USER_VALID: 0x%x\n", mbox_num, rd_data);
     return rd_data;

src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox0_ecc.yml

@@ -0,0 +1,7 @@
+---
+seed: 1
+testname: smoke_test_mcu_mbox0_ecc
+pre-exec: |
+  echo "Running pre_exec for [smoke_test_mcu_mbox_ecc]"
+  CALIPTRA_ROOT=$CALIPTRA_SS_ROOT/third_party/caliptra-rtl make -f $CALIPTRA_SS_ROOT/third_party/caliptra-rtl/tools/scripts/Makefile BUILD_CFLAGS="-DMCU_MBOX_VALID_VECTOR=0x1" CALIPTRA_INTERNAL_TRNG=0 TESTNAME=smoke_test_mbox program.hex
+  make -f $CALIPTRA_SS_ROOT/tools/scripts/Makefile TESTNAME=smoke_test_mcu_mbox_ecc BUILD_CFLAGS="-DMCU_MBOX_VALID_VECTOR=0x1" mcu_program.hex

src/integration/test_suites/smoke_test_mcu_mbox_ecc/smoke_test_mcu_mbox1_ecc.yml

@@ -0,0 +1,7 @@
+---
+seed: 1
+testname: smoke_test_mcu_mbox1_ecc
+pre-exec: |
+  echo "Running pre_exec for [smoke_test_mcu_mbox_ecc]"
+  CALIPTRA_ROOT=$CALIPTRA_SS_ROOT/third_party/caliptra-rtl make -f $CALIPTRA_SS_ROOT/third_party/caliptra-rtl/tools/scripts/Makefile CALIPTRA_INTERNAL_TRNG=0 TESTNAME=smoke_test_mbox BUILD_CFLAGS="-DMCU_MBOX_VALID_VECTOR=0x2" program.hex
+  make -f $CALIPTRA_SS_ROOT/tools/scripts/Makefile TESTNAME=smoke_test_mcu_mbox_ecc BUILD_CFLAGS="-DMCU_MBOX_VALID_VECTOR=0x2" mcu_program.hex