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[VAL] Fix randomization for mask select and SVA conditions #417

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Merged
clayton8 merged 10 commits into from
May 7, 2025
Merged

[VAL] Fix randomization for mask select and SVA conditions #417

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7988fb4
Fix randomization, fix false failures in sva
upadhyayulakiran May 5, 2025
e701a5d
Merge branch 'main' into kupadhyayula-mask-rand
upadhyayulakiran May 5, 2025
351581a
MICROSOFT AUTOMATED PIPELINE: Stamp 'kupadhyayula-mask-rand' with upd…
upadhyayulakiran May 6, 2025
56f48f6
Use xorshift32
upadhyayulakiran May 7, 2025
2294d85
Merge branch 'kupadhyayula-mask-rand' of ssh://github.com/chipsallian…
upadhyayulakiran May 7, 2025
935a8f8
Merge branch 'main' into kupadhyayula-mask-rand
upadhyayulakiran May 7, 2025
d3806be
MICROSOFT AUTOMATED PIPELINE: Stamp 'kupadhyayula-mask-rand' with upd…
upadhyayulakiran May 7, 2025
f6a3837
Merge branch 'main' into kupadhyayula-mask-rand
upadhyayulakiran May 7, 2025
f621b2c
Merge branch 'kupadhyayula-mask-rand' of ssh://github.com/chipsallian…
upadhyayulakiran May 7, 2025
7a5e6b4
MICROSOFT AUTOMATED PIPELINE: Stamp 'kupadhyayula-mask-rand' with upd…
upadhyayulakiran May 7, 2025
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2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_hash
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fb63383aa84c29379d07dc83902f53dd0700d26a44182e4da862b1854955ebbc105748f91f786f296a2796e9727cf937
44ade7dc06089673ec65c7e2cb77918eba9f5df20c2092d6b46ae8564f11553108d9214a86a51b99231bc00ee9ea091b
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_timestamp
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42 changes: 30 additions & 12 deletions src/integration/asserts/caliptra_ss_top_sva.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -233,23 +233,41 @@ module caliptra_ss_top_sva
agg_all_error_fatal_check: assert property (
@(posedge `CPTRA_SS_TB_TOP_NAME.core_clk)
disable iff (~`CPTRA_SS_TOP_PATH.cptra_ss_rst_b_i)
(`CPTRA_SS_TOP_PATH.cptra_error_fatal & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal0 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o) and
(`CPTRA_SS_TOP_PATH.mcu_dccm_ecc_double_error & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal6 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o) and
((`CPTRA_SS_TOP_PATH.lc_alerts_o != 0) & (`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal14 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal13 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal12) |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o) and
((`CPTRA_SS_TOP_PATH.fc_alerts != 0) & (`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal20 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal19 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal18) |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o) and
(`CPTRA_SS_TOP_PATH.i3c_peripheral_reset & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal25 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o) and
(`CPTRA_SS_TOP_PATH.i3c_escalated_reset & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal24 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o)
(((`CPTRA_SS_TOP_PATH.cptra_error_fatal & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal0) |
(`CPTRA_SS_TOP_PATH.mcu_dccm_ecc_double_error & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal6) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[0] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal12) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[1] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal13) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[2] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal14) |
(`CPTRA_SS_TOP_PATH.fc_alerts[0] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal18) |
(`CPTRA_SS_TOP_PATH.fc_alerts[1] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal19) |
(`CPTRA_SS_TOP_PATH.fc_alerts[2] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal20) |
(`CPTRA_SS_TOP_PATH.fc_alerts[3] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal21) |
(`CPTRA_SS_TOP_PATH.fc_alerts[4] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal22) |
(`CPTRA_SS_TOP_PATH.fc_intr_otp_error & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal23) |
(`CPTRA_SS_TOP_PATH.i3c_escalated_reset & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal24) |
(`CPTRA_SS_TOP_PATH.i3c_peripheral_reset & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_fatal_mask.mask_agg_error_fatal25)

) |=> ##2 `CPTRA_SS_TOP_PATH.cptra_ss_all_error_fatal_o)
) else $display("SVA ERROR: AGG all_error_fatal is not set correctly");

agg_all_error_non_fatal_check: assert property (
@(posedge `CPTRA_SS_TB_TOP_NAME.core_clk)
disable iff (~`CPTRA_SS_TOP_PATH.cptra_ss_rst_b_i)
(`CPTRA_SS_TOP_PATH.cptra_error_non_fatal & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal0 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o) and
(`CPTRA_SS_TOP_PATH.mcu_dccm_ecc_single_error & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal6 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o) and
((`CPTRA_SS_TOP_PATH.lc_alerts_o != 0) & (`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal14 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal13 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal12) |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o) and
((`CPTRA_SS_TOP_PATH.fc_alerts != 0) & (`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal20 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal19 | `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal18) |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o) and
(`CPTRA_SS_TOP_PATH.i3c_peripheral_reset & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal25 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o) and
(`CPTRA_SS_TOP_PATH.i3c_escalated_reset & `MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal24 |=> ##2 ~`CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o)
(((`CPTRA_SS_TOP_PATH.cptra_error_non_fatal & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal0) |
(`CPTRA_SS_TOP_PATH.mcu_dccm_ecc_single_error & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal6) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[0] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal12) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[1] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal13) |
(`CPTRA_SS_TOP_PATH.lc_alerts_o[2] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal14) |
(`CPTRA_SS_TOP_PATH.fc_alerts[0] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal18) |
(`CPTRA_SS_TOP_PATH.fc_alerts[1] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal19) |
(`CPTRA_SS_TOP_PATH.fc_alerts[2] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal20) |
(`CPTRA_SS_TOP_PATH.fc_alerts[3] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal21) |
(`CPTRA_SS_TOP_PATH.fc_alerts[4] & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal22) |
(`CPTRA_SS_TOP_PATH.fc_intr_otp_error & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal23) |
(`CPTRA_SS_TOP_PATH.i3c_escalated_reset & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal24) |
(`CPTRA_SS_TOP_PATH.i3c_peripheral_reset & ~`MCI_REG_TOP_PATH.mci_reg_hwif_out.internal_agg_error_non_fatal_mask.mask_agg_error_non_fatal25)

) |=> ##2 `CPTRA_SS_TOP_PATH.cptra_ss_all_error_non_fatal_o)
) else $display("SVA ERROR: AGG all_error_non_fatal is not set correctly");

//----------------------------------------------
Expand Down
26 changes: 9 additions & 17 deletions src/integration/test_suites/smoke_test_error_handling/smoke_test_error_handling.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,12 +35,6 @@ volatile uint32_t rst_count = 0;
enum printf_verbosity verbosity_g = LOW;
#endif

#ifdef PLAYBOOK_RANDOM_SEED
unsigned time = (unsigned) PLAYBOOK_RANDOM_SEED;
#else
unsigned time = 0;
#endif

volatile uint32_t * mci_error0_intr_en = (uint32_t *) SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R; //TODO: confirm
volatile uint32_t * mci_error1_intr_en = (uint32_t *) SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_ERROR1_INTR_EN_R;
volatile uint32_t * mci_notif0_intr_en = (uint32_t *) SOC_MCI_TOP_MCI_REG_INTR_BLOCK_RF_NOTIF0_INTR_EN_R;
Expand Down Expand Up @@ -109,15 +103,13 @@ void service_notif0_intr() {
}

uint32_t main(void) {
uint8_t rand_mask_sel;
uint32_t rand_mask_sel;
uint32_t data = 0;

VPRINTF(LOW, "---------------------------\n");
VPRINTF(LOW, " Err Handling Smoke Test\n");
VPRINTF(LOW, "---------------------------\n");

srand(time);

//Enable SOC notif interrupt
*mci_error0_intr_en = MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_MCU_SRAM_DMI_AXI_COLLISION_EN_MASK | MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_INTERNAL_EN_MASK | MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_MBOX0_ECC_UNC_EN_MASK | MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_MBOX1_ECC_UNC_EN_MASK | MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK | MCI_REG_INTR_BLOCK_RF_ERROR0_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK;
*mci_error1_intr_en = 0xffff;
Expand All @@ -144,7 +136,7 @@ uint32_t main(void) {
}
else if (rst_count == 2) {
VPRINTF(LOW, "------------\nMCI err with mask\n------------\n");
rand_mask_sel = rand() % 0x8; //% 8 since there are 3 mask bits and 2**3 combinations
rand_mask_sel = xorshift32() % 0x8; //% 8 since there are 3 mask bits and 2**3 combinations
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_FATAL_MASK, rand_mask_sel);
SEND_STDOUT_CTRL(TB_CMD_INJECT_MCI_ERROR_FATAL);

Expand All @@ -169,7 +161,7 @@ uint32_t main(void) {

//Add other stuff here
VPRINTF(LOW, "------------\nMCI non-ftl err with mask\n------------\n");
rand_mask_sel = rand() % 0x4; //% 4 since there are 2 mask bits and 2**2 combinations
rand_mask_sel = xorshift32() % 0x4; //% 4 since there are 2 mask bits and 2**2 combinations
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_HW_ERROR_NON_FATAL_MASK, rand_mask_sel);
SEND_STDOUT_CTRL(TB_CMD_INJECT_MCI_ERROR_NON_FATAL);

Expand All @@ -190,7 +182,7 @@ uint32_t main(void) {
}
else if (rst_count == 4) {
VPRINTF(LOW, "-------------\nAggregate ftl err with mask\n---------------\n");
rand_mask_sel = rand() % 32;
rand_mask_sel = xorshift32();
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_FATAL_MASK, rand_mask_sel);
SEND_STDOUT_CTRL(TB_CMD_INJECT_AGG_ERROR_FATAL);

Expand All @@ -214,7 +206,7 @@ uint32_t main(void) {
}
else if (rst_count == 6) {
VPRINTF(LOW, "-------------\nAggregate non ftl err with mask\n---------------\n");
rand_mask_sel = rand() % 32;
rand_mask_sel = xorshift32();
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_AGG_ERROR_NON_FATAL_MASK, rand_mask_sel);
SEND_STDOUT_CTRL(TB_CMD_INJECT_AGG_ERROR_NON_FATAL);

Expand All @@ -227,8 +219,8 @@ uint32_t main(void) {
}
else if (rst_count == 7) {
VPRINTF(LOW, "-------------\nFW ftl/non-ftl err without mask\n---------------\n");
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL, rand());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL, rand());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL, xorshift32());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL, xorshift32());

for(uint8_t i = 0; i < 10; i++);
SEND_STDOUT_CTRL(TB_CMD_WARM_RESET);
Expand All @@ -239,8 +231,8 @@ uint32_t main(void) {
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_FATAL_MASK, 0xffff);
lsu_write_32(SOC_MCI_TOP_MCI_REG_INTERNAL_FW_ERROR_NON_FATAL_MASK, 0xffff);

lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL, rand());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL, rand());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_FATAL, xorshift32());
lsu_write_32(SOC_MCI_TOP_MCI_REG_FW_ERROR_NON_FATAL, xorshift32());

for(uint8_t i = 0; i < 10; i++);
SEND_STDOUT_CTRL(TB_CMD_WARM_RESET);
Expand Down
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