[WIP] [RTL] Integrate dcls and traces#634
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mtdudek wants to merge 4 commits intochipsalliance:mainfrom
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[WIP] [RTL] Integrate dcls and traces#634mtdudek wants to merge 4 commits intochipsalliance:mainfrom
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Add trace mux to select between MCU, caliptra-top main, and caliptra-top shadow cores. Add registers to control DCLS error detection and error injection. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
Caliptra-rtl modified 'reg_doc_gen.py' and it is no longer compatible with the caliptra-ss structure. Caliptra-rtl commit 86fe5b6 This commit creates copy of the caliptr-rtl script before changes. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
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a. Mux CSR is available through TAP interface
security_state_o.debug_lockedtools/scripts/gen_soc_regs.shas it stopped working after recent changes to the caliptra-rtlDepends on the PR in caliptra-rtl
chipsalliance/caliptra-rtl#737