Caliptra Subsystem 0.8 Release

Release_Notes.md

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+# Caliptra Subsystem 0.8 Release Notes
+
+## 1. Caliptra Core
+- Adams Bridge
+- PQC Key Vault & Derivation Support
+- OCP Recovery Support
+- Updated VeeR core pointing to VeeR 2.0 release
+- Increased ROM, ICCM/DCCM, and Mailbox sizes for Caliptra 2.0
+- Manufacturing Debug Unlock Support
+- Production Debug Unlock Support
+- All bug fixes since Caliptra core freeze
+
+## 2. I3C
+- Compliant with:
+  - MIPI Alliance Specification for I3C Basic, Version 1.1.1
+  - MIPI Alliance Specification for I3C HCI, Version 1.2
+  - MIPI Alliance Specification for I3C TCRI, Version 1.0
+- Operational in both Active and Secondary Controller Modes
+- Caliptra subsystem uses only target/secondary controller mode
+- OCP Recovery Support
+
+## 3. Life Cycle Controller (LCC)
+- Spec-documented LC states and transitions
+- Multiple test unlock tokens for supply chain protection
+- Physical presence detection capability for RMA
+
+## 4. Fuse Controller (FC)
+- Caliptra core fuse map spec to Jan 10, 2025
+- Production Debug Unlock Support
+- Multi-test unlock token support
+- Manufacturing time generic secret fuses for SoC usage
+
+## 5. Manufacturer Control Unit (MCU):
+  - A dedicated VeeR instance for SoC-specific firmware
+  - PmP & User Mode Enabled
+
+## 6. Manufacturer Control Interface (MCI):
+  - Caliptra Subsystem Boot Sequencer
+  - MCU SRAM with ECC
+  - Caliptra SS Registers
+  - Caliptra SS RAS Support
+  - MCU Mailboxes
+  - Caliptra Core LCC State Translator
+  - SoC Manufacturing Debug Unlock Support
+  - SoC Production Debug Unlock Support
+  - MCU ROM Interface Module
+
+## Basic validation flows completed for:
+  - Recovery flow over I3C
+  - DMA from Caliptra to/from MCI
+  - MCU interaction with all the blocks (I3C, Caliptra, LCC, FC, MCU ROM, and MCI)
+  - Life Cycle Controller interactions and life cycle state changes
+  - Life Cycle Controller & Fuse Controller interactions
+
+## Known Items
+- Toolset for adding Generic SoC fuses & Generic IFP Secret fuses for SoC usage
+- Regen FC for 1/16/2025 Caliptra core spec update
+- I3C high frequency domain configuration parameters testing work in progress 
+- Adams bridge memory ports
+- Lint fixes

config/compilespecs.yml

@@ -12,6 +12,7 @@ files:
   - src/lc_ctrl/config/compile.yml
   - src/fuse_ctrl/config/compile.yml
   - src/mci/config/compile.yml
+  - src/axi_mem/config/compile.yml
   - src/integration/config/avery_vip.yml
   - third_party/caliptra-rtl/src/libs/config/compile.yml
   - third_party/caliptra-rtl/src/ahb_lite_bus/config/compile.yml

src/axi_mem/config/compile.yml

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+provides: [axi_mem_pkg]
+schema_version: 2.4.0
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/axi_mem_if.sv
+      - $COMPILE_ROOT/rtl/axi_mem.sv
+  tb:
+    directories: [$COMPILE_ROOT/testbench]
+    files:
+      - $COMPILE_ROOT/rtl/axi_mem_if.sv
+      - $COMPILE_ROOT/rtl/axi_mem.sv
+      - $COMPILE_ROOT/testbench/rom.sv

src/axi_mem/rtl/axi_mem.sv

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+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+module axi_mem #(
+    parameter AW = 32,
+    parameter DW = 64,
+              BC = DW/8,       // Byte Count
+              BW = $clog2(BC), // Byte count Width
+    parameter UW = 32,         // User Width
+    parameter IW = 1,          // ID Width
+              ID_NUM = 1 << IW, // Don't override
+
+    parameter EX_EN = 0    // Enable exclusive access tracking w/ AxLOCK
+)
+(
+    input clk,
+    input rst_n,
+
+    // AXI INF
+    axi_if.w_sub s_axi_w_if,
+    axi_if.r_sub s_axi_r_if,
+
+    //COMPONENT INF
+    axi_mem_if.request s_mem_req_if
+);
+
+//COMPONENT INF
+logic          dv;
+logic [AW-1:0] addr; // Byte address
+logic          write;
+logic [DW-1:0] wdata; // Requires: Component dwidth == AXI dwidth
+logic [DW-1:0] rdata; // Requires: Component dwidth == AXI dwidth
+logic          hold;
+logic          rd_error;
+logic          wr_error;
+
+
+axi_sub #(
+    .AW   (AW   ),
+    .DW   (DW   ),
+    .UW   (UW   ),
+    .IW   (IW   ),
+    .EX_EN(EX_EN),
+    .C_LAT(1    )
+) i_axi_sub (
+    .clk  (clk     ),
+    .rst_n(rst_n   ),
+
+    // AXI INF
+    .s_axi_w_if(s_axi_w_if),
+    .s_axi_r_if(s_axi_r_if),
+
+    //COMPONENT INF
+    .dv      (dv      ),
+    .addr    (addr    ), // Byte address
+    .write   (write   ),
+    .user    (        ),
+    .id      (        ),
+    .wdata   (wdata   ),
+    .wstrb   (        ),
+    .rdata   (rdata   ),
+    .last    (        ),
+    .size    (        ),
+    .hld     (hold    ),
+    .rd_err  (rd_error),
+    .wr_err  (wr_error)
+);
+
+assign hold = 1'b0;
+assign rd_error = 1'b0;
+assign wr_error = 1'b0;
+
+assign s_mem_req_if.req.cs   = dv;
+assign s_mem_req_if.req.we   = write;
+assign s_mem_req_if.req.addr = addr[AW-1:BW];
+assign s_mem_req_if.req.wdata.data = wdata;
+assign rdata = s_mem_req_if.resp.rdata.data;
+
+endmodule

src/axi_mem/rtl/axi_mem_if.sv

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+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// Description:
+//      Signals for an SRAM interface with ECC
+//
+
+interface axi_mem_if #(parameter integer ADDR_WIDTH = 16, parameter integer DATA_WIDTH = 32) (input logic clk, input logic rst_b);
+
+    // SRAM data
+    typedef struct packed {
+        logic [DATA_WIDTH-1:0]  data;
+    } sram_data_t;
+
+    // Request to sram
+    typedef struct packed {
+        logic cs;
+        logic we;
+        logic [ADDR_WIDTH-1:0] addr;
+        sram_data_t wdata;
+    } sram_req_t;
+
+    // Response from sram
+    typedef struct packed {
+        sram_data_t rdata;
+    } sram_resp_t;
+
+    sram_req_t req;
+
+    sram_resp_t resp;
+
+    // Requester interface (typically on AXI module)
+    modport request (
+
+        // Request to SRAM
+        output  req,
+
+        // Response from SRAM
+        input   resp
+    );
+
+    // Response interface (typically on SRAM)
+    modport response (
+        // Request to SRAM
+        input  req,
+
+        // Response from SRAM
+        output   resp
+    );
+
+endinterface

src/axi_mem/testbench/rom.sv

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+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module rom #(
+     parameter DEPTH      = 64
+    ,parameter DATA_WIDTH = 32
+    ,parameter ADDR_WIDTH = $clog2(DEPTH)
+
+    )
+    (
+    input  logic                       clk_i,
+
+    input  logic                       cs_i,
+    input  logic                       we_i,
+    input  logic [ADDR_WIDTH-1:0]      addr_i,
+    input  logic [DATA_WIDTH-1:0]      wdata_i,
+    output logic [DATA_WIDTH-1:0]      rdata_o
+    );
+
+    localparam NUM_BYTES = DATA_WIDTH/8 + ((DATA_WIDTH % 8) ? 1 : 0);
+
+    //storage element
+    logic [7:0] ram [DEPTH][NUM_BYTES-1:0];
+
+    always @(posedge clk_i) begin
+        if (cs_i & we_i) begin
+            for (int i = 0; i < NUM_BYTES; i++) begin
+                ram[addr_i][i] <= wdata_i[i*8 +: 8];
+            end
+        end
+        if (cs_i & ~we_i) begin
+            for (int i = 0; i < NUM_BYTES; i++) begin
+                rdata_o[i*8 +: 8] <= ram[addr_i][i];
+            end
+        end
+    end
+
+endmodule