Caliptra Subsystem 0.8 Release

src/fuse_ctrl/rtl/otp_ctrl.sv

@@ -39,12 +39,8 @@ module otp_ctrl
   input axi_struct_pkg::axi_rd_req_t                  core_axi_rd_req,
   output axi_struct_pkg::axi_rd_rsp_t                 core_axi_rd_rsp,
 
-  // input  tlul_pkg::tl_h2d_t                          prim_tl_i,
-  // output tlul_pkg::tl_d2h_t                          prim_tl_o,
-  // input axi_struct_pkg::axi_wr_req_t                  prim_axi_wr_req,
-  // output axi_struct_pkg::axi_wr_rsp_t                 prim_axi_wr_rsp,
-  // input axi_struct_pkg::axi_rd_req_t                  prim_axi_rd_req,
-  // output axi_struct_pkg::axi_rd_rsp_t                 prim_axi_rd_rsp,
+  input  tlul_pkg::tl_h2d_t                          prim_tl_i,
+  output tlul_pkg::tl_d2h_t                          prim_tl_o,
 
   // Interrupt Requests
   output logic                                       intr_otp_operation_done_o,
@@ -166,61 +162,6 @@ module otp_ctrl
       .tl_i           (core_tl_o)
   );
 
-  // Prim AXI2TLUL interface signals
-  tlul_pkg::tl_h2d_t      prim_tl_i;
-  tlul_pkg::tl_d2h_t      prim_tl_o;
-
-
-  axi_struct_pkg::axi_wr_req_t prim_axi_wr_req;
-  axi_struct_pkg::axi_wr_rsp_t prim_axi_wr_rsp;
-  axi_struct_pkg::axi_rd_req_t prim_axi_rd_req;
-  axi_struct_pkg::axi_rd_rsp_t prim_axi_rd_rsp;
-
-  axi_if prim_axi_if(
-    .clk(clk_i),
-    .rst_n(rst_ni)
-  );
-
-  assign prim_axi_if.awaddr      = '0;
-  assign prim_axi_if.awburst     = '0;
-  assign prim_axi_if.awsize      = '0;
-  assign prim_axi_if.awlen       = '0;
-  assign prim_axi_if.awuser      = '0;
-  assign prim_axi_if.awid        = '0;
-  assign prim_axi_if.awlock      = '0;
-  assign prim_axi_if.awvalid     = '0;
-
-  assign prim_axi_if.wdata       = '0;
-  assign prim_axi_if.wstrb       = '0;
-  assign prim_axi_if.wlast       = '0;
-  assign prim_axi_if.wvalid      = '0;
-
-  assign prim_axi_if.bready      = '0;
-
-  assign prim_axi_if.araddr      = '0;
-  assign prim_axi_if.arburst     = '0;
-  assign prim_axi_if.arsize      = '0;
-  assign prim_axi_if.arlen       = '0;
-  assign prim_axi_if.aruser      = '0;
-  assign prim_axi_if.arid        = '0;
-  assign prim_axi_if.arlock      = '0;
-  assign prim_axi_if.arvalid     = '0;
-  assign prim_axi_if.rready      = '0;
-
-  // Prim AXI2TLUL instance
-  axi2tlul #(
-      .AW     (32),
-      .DW     (32),
-      .UW     (32),
-      .IW     (8 )
-  ) u_prim_axi2tlul (
-      .clk            (clk_i),
-      .rst_n          (rst_ni),
-      .s_axi_w_if     (prim_axi_if.w_sub),
-      .s_axi_r_if     (prim_axi_if.r_sub),
-      .tl_o           (prim_tl_i),
-      .tl_i           (prim_tl_o)
-  );
 
 
 
@@ -1703,4 +1644,4 @@ end
         u_otp.u_reg_top, alert_tx_o[3])
     //    //u_otp.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3])
   end
-endmodule : otp_ctrl
+endmodule : otp_ctrl

src/integration/config/compile.yml

@@ -1,16 +1,44 @@
+---
+provides: [caliptra_ss_top_defines]
+schema_version: 2.4.0
+targets:
+  tb:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/soc_address_map_defines.svh
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/soc_address_map_defines.svh
+---
 provides: [caliptra_ss_top]
 schema_version: 2.4.0
 requires:
+  - caliptra_ss_top_defines
   - caliptra_ss_lc_ctrl_pkg
-  - lc_ctrl
-  - mcu_top
   - css_mcu0_veer_el2_rtl_pkg
-  - i3c-core
   - tlul_pkg
   - fuse_ctrl_pkg
+  - lc_ctrl
+  - mcu_top
+  - i3c-core
   - fuse_ctrl
-  - caliptra_top_tb_pkg
   - mci_top
+targets:
+  rtl:
+    directories: 
+      - $COMPILE_ROOT/rtl
+    files:
+      - $COMPILE_ROOT/rtl/caliptra_ss_top.sv
+    tops: [caliptra_ss_top]
+--- 
+provides: [caliptra_ss_top_tb]
+schema_version: 2.4.0
+requires:
+  - caliptra_ss_lc_ctrl_pkg
+  - caliptra_ss_top_defines
+  - caliptra_ss_top
+  - caliptra_top_tb_pkg
   - avery_vip
 targets:
   tb:
@@ -28,12 +56,11 @@ targets:
       # - $COMPILE_ROOT/testbench/dasm.svi
       - $COMPILE_ROOT/testbench/mci_sram.sv
       - $COMPILE_ROOT/testbench/aaxi_pkg_caliptra_test.sv
-      - $COMPILE_ROOT/rtl/soc_address_map_defines.svh
       - $COMPILE_ROOT/testbench/aaxi4_interconnect.sv
       - $COMPILE_ROOT/testbench/fuse_ctrl_bfm.sv
       - $COMPILE_ROOT/testbench/lc_ctrl_bfm.sv
-      - $COMPILE_ROOT/testbench/caliptra_ss_top.sv
-    tops: [caliptra_ss_top, ai3c_tests_bench]
+      - $COMPILE_ROOT/testbench/caliptra_ss_top_tb.sv
+    tops: [caliptra_ss_top_tb, ai3c_tests_bench]
   sim:
     pre_exec: '$MSFT_SCRIPTS_DIR/run_test_makefile && echo "[PRE-EXEC] Copying ECC vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/ecc/tb/ecc_secp384r1.exe . 
                 && echo "[PRE-EXEC] Copying DOE vector generator to ${pwd}" && cp $COMPILE_ROOT/../../third_party/caliptra-rtl/src/doe/tb/doe_test_gen.py .
@@ -50,12 +77,13 @@ global:
         - '-sverilog -full64'
         - '-debug_access+all'
         # Used in caliptra_top_sva to find signals
-        - +define+CPTRA_TB_TOP_NAME=caliptra_ss_top
-        - +define+CPTRA_TOP_PATH=caliptra_ss_top.caliptra_top_dut
+        - +define+CPTRA_TB_TOP_NAME=caliptra_ss_top_tb
+        - +define+CPTRA_TOP_PATH=caliptra_ss_top_tb.caliptra_ss_dut.caliptra_top_dut
         - +define+MCU_RV_BUILD_AXI4
         - +define+MCU_RV_OPENSOURCE
         - +define+AVERY_VCS
         - +define+AVERY_CLOCK=5
+        - +define+LCC_FC_BFM_SIM=1 # this is a defined to enable LCC BFM reset to be driven to LCC and FC
         - +define+FOUR_OUTSTANDING
         - +define+AVERY_AXI_INTERCONNECT
         - +define+AAXI_MAX_DATA_WIDTH=64