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Verilog: casts from real to int #1138

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Merged
merged 1 commit into from
Jun 4, 2025
Merged

Verilog: casts from real to int #1138

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3 changes: 1 addition & 2 deletions regression/verilog/expressions/cast_from_real2.desc
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Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
KNOWNBUG
CORE
cast_from_real2.sv

^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
The implicit cast is currently not allowed.
8 changes: 8 additions & 0 deletions src/verilog/verilog_typecheck_expr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2123,6 +2123,14 @@ void verilog_typecheck_exprt::implicit_typecast(
expr = typecast_exprt{expr, dest_type};
return;
}
else if(
dest_type.id() == ID_bool || dest_type.id() == ID_signedbv ||
dest_type.id() == ID_unsignedbv)
{
// Cast from float to int -- the rounding mode is added during lowering.
expr = typecast_exprt{expr, dest_type};
return;
}
}
else if(src_type.id() == ID_verilog_null)
{
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