Skip to content

Verilog: fix for named generate block scopes #1150

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
tautschnig merged 1 commit into from
Jun 16, 2025

Verilog: fix for named generate block scopes

4f35181
Select commit
Loading
Failed to load commit list.
Sign in for the full log view
Merged

Verilog: fix for named generate block scopes #1150

Verilog: fix for named generate block scopes
4f35181
Select commit
Loading
Failed to load commit list.

The logs for this run have expired and are no longer available.