Intel architecture improvements for .NET 10

[BruceForstall]

This issue describes planned improvements to Intel architecture (x86, x64) ISA support for .NET 10.

The primary addition will be APX support, which is expected to be available in .NET 10 but considered "Experimental", and possibly requiring explicit opt-in via some kind of configuration option, pending available hardware, testing, and completion status.

For reference, here is the corresponding .NET 9 issue for Intel architecture improvements: #93196

APX

APX is a new ISA extension (see here for a summary and links to specifications). Notably, it doubles the number of general-purpose registers from 16 to 32, as well as adding new encodings and instructions.

There is an "apx" label that should be added to any APX related GitHub issue. Here is a query showing all such issues: apx Related to the Intel Advanced Performance Extensions (APX) .

Work items:

Basic support: CPUID detection, encodings

• Enable CPUID detection and XSAVE features. PR: Update the CPUID and XSAVE logics for APX #104637.
• Enable REX2 encoding to use EGPRs. PR: [JIT] Enable EGPRs in JIT by adding REX2 encoding to the backend. #106557.
• [APX-REX2] Left-over TODOs after REX2 encoding changes. [APX-REX2] Left-over TODOs after REX2 encoding changes #110414
• Enable EVEX encoding promotion for legacy instructions. PR: [JIT] Add legacy extended EVEX encoding and EVEX.ND/NF feature to x64 emitter backend #108796.
• Enable EVEX NF form encoding promotion for legacy instructions.
• Enable VEX/EVEX encoding to use EGPRs
• Add remaining APX NCI instructions to emitter. Add remaining APX NCI instructions to emitter #114563

Conditional instructions

• Implement if-conversion optimizations (utilize existing peephole and ARM lowering)
• Add new conditional instructions (CCMP, CFCMOV, etc.). [JIT] Enable conditional chaining for Intel APX #111072
• [Q2'2025] Tune conditional compare optimizations for APX. Tune conditional compare optimizations for APX #114564

Register allocation (LSRA)

• Upgrade LSRA to allow EGPRs when APX is available. PR: [JIT] [APX] Enable additional General Purpose Registers. #108799.
• [Q2'2025] Improve LSRA to handle more than 64 registers for x64. Improve LSRA to handle more than 64 registers for x64 #112959
• [Q2'2025] Tune LSRA with APX EGPR. Tune LSRA with APX EGPR #114561

Push2/pop2

• [Q2'2025] Track APX push2/pop2 OS changes for .NET unwinder changes. Track APX push2/pop2 OS changes for .NET unwinder changes #112762
• [Q2'2025] Enable and optimize LSRA with APX push2/pop2. Enable and optimize LSRA with APX push2/pop2 #114560

Uncategorized

• [Q2'2025] Enable EGPR for GenTree nodes that lower to promoted VEX/EVEX encoding. Enable EGPR for GenTree nodes that lower to promoted VEX/EVEX encoding. #114559
• [Q2'2025] Optimize and tune APX NDD form codegen. Optimize and tune APX NDD form codegen #114562

Non-JIT: P/Invoke, GC info, diagnostics

• Add CI support for testing APX Add CI support for testing APX #110672
• Diagnostics support. Support breakpoints on APX instructions #112588. Implement breakpoint disassembly support for Intel APX #114120.
• [Q2'2025] Address APX requirements for GC and VM stubs. Address APX requirements for GC and VM stubs #112587
• Investigate P/Invoke implications of eGPRs
• [Q2'2025] Get ThreadContext for APX extended registers. [APX] Get ThreadContext for APX extended registers #112757

AVX10

• Allow embedded rounding for YMM/ZMM (related: Enable EVEX embedded rounding support in xarch emitter #93154) (Owner: Intel, Starting AVX10.2)
• [AVX10.2]Optimize codegen for x86 using the new saturating conversion instructions when possible [AVX10.2]Optimize codegen for x86 using the new saturating conversion instructions when possible. #109080
• [AVX10.2]Optimize codegen for x86 using the new minmax instructions when possible [AVX10.2]Optimize codegen for x86 using the new minmax instructions when possible. #109081
• (Help Wanted) Convert remaining AVX2 implementations to Vector256 Switching to Vectors from target dependent instrinsics #101251

AVX10v2 API design

• [API Proposal]: Add AVX10v2 API to add Avx10.2 support [API Proposal]: Add AVX10v2 API to add Avx10.2 support #109083
• [API Proposal]: Add dot product intrinsics to AVX10v2 API [API Proposal]: Add dot product intrinsics to AVX10v2 API #110032

General API design

• [API Proposal]: Add AVX10v2 API to add Avx10.2 support #109083 - AVX10v2
• [Q2'2025] [API Proposal]: Add AVX-VNNI-INT8 and AVX-VNNI-INT16 API #112586 - AVX-VNNI-INT8 and AVX-VNNI-INT16

Bugs and uncategorized work

• [Q2'2025] Suboptimal stack zeroing on AVX512. Suboptimal stack zeroing on AVX512 #114274
• [Q2'2025] More folding to vpternlogd. More folding to vpternlogd? #107619

Future work

The following work was pushed to the future.

General API design

• [API Proposal]: : AVX-IFMA Intrinsics #98833 - AVX-IFMA
• [API Proposal]: Expose AVX512 FP16 and AVX F16C ISA #98820 - AVX512 FP16 + AVX F16C
• [API Proposal]: AVX-512 IFMA Intrinsics #96476 - AVX512-IFMA
• [API Proposal]: AVX-512 VPOPCNTDQ and BITALG Intrinsics #96162 - VPOPCNTDQ + BTALG
• [API Proposal]: Expose System.Runtime.Intrinsics.X86.Aes256 and Aes512 #86952 - AES256 + AES512
• [API Proposal]: Add support for AVX-512 VNNI hardware instructions #86849 - AVX512-VNNI
• Using UMONITOR, UMWAIT, TPAUSE in CLR and exposing in Intel specific hardware intrinsics #66873 - WAITPKG

Libraries work

• Light up IndexOfAnyAsciiSearcher for AVX512. Light up IndexOfAnyAsciiSearcher for AVX512 #93222 (@MihaZupan)
• (Help Wanted) Light up Utf8/Utf16 code with Vector512. Light up Utf8Utility.*.cs and Utf16Utility.*.cs with Vector512 code paths.  #86119
• (Help Wanted) Light up Ascii.Utility methods with Vector512 code paths. Light up Ascii.Utility methods with Vector512 code paths. #89280
  • Switch to iSimdVector and Align WidenAsciiToUtf16 #99982
  • Light up core ASCII.Utility methods with Vector256/Vector512 code paths. #88532
  • Use StoreAligned not Store in WidenAsciiToUtf16 #89892

RyuJIT feature work

• Vector512.Dot: AVX-512 specific light-up for Vector512.Dot Finish Avx512 specific lightup for Vector128/256/512<T> #85207

Vector<T>

• Consider Vector<T> expanding to Vector512<T>, either automatically or opt-in. (@tannergooding plans to get back to it as a best effort.)

JCC erratum

• RyuJIT: Implement mitigation for Intel JCC erratum #93243 (TBD)

Debugging / diagnostics work (@BruceForstall)

• AVX-512 debugger support: view registers #87854 (and related work for APX)

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[JulieLeeMSFT]

Changed the assignee for the JCC erratum to TBD.
#93243