Skip to content

JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar #103847

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
TIHan wants to merge 20 commits into from
Closed

JIT: ARM64 - Added SVE APIs ExtractLastVector, ExtractLastScalar, ExtractAfterLastVector, ExtractAfterLastScalar #103847

Show file tree
Hide file tree
Changes from 5 commits
Commits
Show all changes
20 commits
Select commit Hold shift + click to select a range
59c5187
ExtractLastVector, ExtractAfterLastVector, ExtractLastScalar, Extract…
TIHan Jun 22, 2024
32c90d0
Special handling for ExtractLastScalar and ExtractAfterLastScalar
TIHan Jun 22, 2024
725d73d
Few tweaks
TIHan Jun 22, 2024
2fe7714
Handling float
TIHan Jun 22, 2024
b23e622
Merge branch 'main' into sve-extract-apis
TIHan Jun 22, 2024
7210af0
Formatting
TIHan Jun 22, 2024
5e6b9d9
Feedback
TIHan Jun 24, 2024
2125977
Feedback
TIHan Jun 24, 2024
23282da
Removing flag
TIHan Jun 24, 2024
353aeb9
Merge branch 'main' into sve-extract-apis
TIHan Jun 24, 2024
3726a22
remove return
TIHan Jun 24, 2024
66ce083
Cleanup
TIHan Jun 24, 2024
a208c15
Merging
TIHan Jun 25, 2024
1374fcb
Feedback
TIHan Jun 26, 2024
fc4a2e2
Trying to fix conditional-select
TIHan Jun 27, 2024
ce5cd51
Merging with main
TIHan Jun 27, 2024
042ee87
Revert some changes
TIHan Jun 27, 2024
90c65bc
Reverting test changes
TIHan Jun 27, 2024
3b88ec7
minor cleanup
TIHan Jun 27, 2024
f122401
Formatting
TIHan Jun 27, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 31 additions & 3 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -490,6 +490,18 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
assert(!instrIsRMW);

insScalableOpts soptEmb = INS_SCALABLE_OPTS_NONE;
switch (intrinEmbMask.id)
{
case NI_Sve_ExtractAfterLastVector:
case NI_Sve_ExtractLastVector:
soptEmb = INS_SCALABLE_OPTS_WITH_SIMD_SCALAR;
break;

default:
break;
}

if (targetReg != falseReg)
{
// If targetReg is not the same as `falseReg` then need to move
Expand All @@ -511,7 +523,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
// If falseValue is zero, just zero out those lanes of targetReg using `movprfx`
// and /Z
GetEmitter()->emitIns_R_R_R(INS_sve_movprfx, emitSize, targetReg, maskReg, targetReg,
opt);
opt, soptEmb);
}
}
else if (emitter::isVectorRegister(embMaskOp1Reg) && (targetReg == embMaskOp1Reg))
Expand All @@ -522,7 +534,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)

// We cannot use use `movprfx` here to move falseReg to targetReg because that will
// overwrite the value of embMaskOp1Reg which is present in targetReg.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt,
soptEmb);

GetEmitter()->emitIns_R_R_R_R(INS_sve_sel, emitSize, targetReg, maskReg, targetReg,
falseReg, opt);
Expand All @@ -536,7 +549,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
}
}

GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt, soptEmb);
break;
}

Expand Down Expand Up @@ -2097,6 +2110,21 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_ExtractAfterLastScalar:
case NI_Sve_ExtractLastScalar:
assert(op1Reg != REG_NA); // this is the embedded mask
assert(op2Reg != REG_NA);

if (varTypeIsFloating(node))
{
GetEmitter()->emitIns_R_R_R(ins, EA_SCALABLE, targetReg, /* mask */ op1Reg, op2Reg, opt, INS_SCALABLE_OPTS_WITH_SIMD_SCALAR);
}
else
{
GetEmitter()->emitIns_R_R_R(ins, emitTypeSize(node), targetReg, /* mask */ op1Reg, op2Reg, opt);
}
break;

case NI_Sve_InsertIntoShiftedVector:
{
assert(isRMW);
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,10 @@ HARDWARE_INTRINSIC(Sve, CreateWhileLessThanOrEqualMask8Bit,
HARDWARE_INTRINSIC(Sve, Divide, -1, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sdiv, INS_sve_udiv, INS_sve_sdiv, INS_sve_udiv, INS_sve_fdiv, INS_sve_fdiv}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, DotProduct, -1, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sdot, INS_sve_udot, INS_sve_sdot, INS_sve_udot, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(Sve, DotProductBySelectedScalar, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sdot, INS_sve_udot, INS_sve_sdot, INS_sve_udot, INS_invalid, INS_invalid}, HW_Category_SIMDByIndexedElement, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_LowVectorOperation)
HARDWARE_INTRINSIC(Sve, ExtractAfterLastScalar, -1, -1, false, {INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, ExtractAfterLastVector, -1, -1, false, {INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta, INS_sve_lasta}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, ExtractLastScalar, -1, -1, false, {INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, ExtractLastVector, -1, -1, false, {INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb, INS_sve_lastb}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, FusedMultiplyAdd, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmla, INS_sve_fmla}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(Sve, FusedMultiplyAddBySelectedScalar, -1, 4, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fmla, INS_sve_fmla}, HW_Category_SIMDByIndexedElement, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_FmaIntrinsic|HW_Flag_LowVectorOperation)
HARDWARE_INTRINSIC(Sve, FusedMultiplyAddNegated, -1, -1, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fnmla, INS_sve_fnmla}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_FmaIntrinsic|HW_Flag_SpecialCodeGen)
Expand Down
44 changes: 35 additions & 9 deletions src/coreclr/jit/lowerarmarch.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1309,17 +1309,43 @@ GenTree* Lowering::LowerHWIntrinsic(GenTreeHWIntrinsic* node)
unsigned simdSize = node->GetSimdSize();
var_types simdType = Compiler::getSIMDTypeForSize(simdSize);
GenTree* trueMask = comp->gtNewSimdAllTrueMaskNode(simdBaseJitType, simdSize);
GenTree* trueVal = node;
GenTree* falseVal = comp->gtNewZeroConNode(simdType);

GenTreeHWIntrinsic* condSelNode =
comp->gtNewSimdHWIntrinsicNode(simdType, trueMask, trueVal, falseVal, NI_Sve_ConditionalSelect,
simdBaseJitType, simdSize);
switch (intrinsicId)
{
// These are special cases where we need to handle the embedded mask differently
// because ConditionalSelect expects a vector, but these APIs return a scalar.
case NI_Sve_ExtractLastScalar:
case NI_Sve_ExtractAfterLastScalar:
{
// Create the same node with an additional operand to pass the mask.
GenTreeHWIntrinsic* newNode =
comp->gtNewSimdHWIntrinsicNode(node->TypeGet(), trueMask, node->Op(1), intrinsicId,
simdBaseJitType, simdSize);

BlockRange().InsertAfter(node->Op(1), trueMask);
BlockRange().InsertAfter(trueMask, newNode);
BlockRange().Remove(node);
use.ReplaceWith(newNode);

node = newNode;
}
break;

BlockRange().InsertBefore(node, trueMask);
BlockRange().InsertBefore(node, falseVal);
BlockRange().InsertAfter(node, condSelNode);
use.ReplaceWith(condSelNode);
default:
{
GenTree* trueVal = node;
GenTree* falseVal = comp->gtNewZeroConNode(simdType);
GenTreeHWIntrinsic* condSelNode =
comp->gtNewSimdHWIntrinsicNode(simdType, trueMask, trueVal, falseVal,
NI_Sve_ConditionalSelect, simdBaseJitType, simdSize);

BlockRange().InsertBefore(node, trueMask);
BlockRange().InsertBefore(node, falseVal);
BlockRange().InsertAfter(node, condSelNode);
use.ReplaceWith(condSelNode);
}
break;
}
}
}
}
Expand Down
Loading