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Merged
merged 7 commits into from
May 29, 2025
Merged

arm64: Rename SVE Prefetch APIs names to use Bit #115609

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68e4272
arm64: Rename SVE Prefetch APIs names to use Bit
jonathandavies-arm May 15, 2025
ceaf0f0
Update src/coreclr/jit/hwintrinsiclistarm64sve.h
kunalspathak May 16, 2025
6d996c6
Update src/coreclr/jit/hwintrinsiclistarm64sve.h
kunalspathak May 16, 2025
e659dc9
Reorder constants & functions
jonathandavies-arm May 19, 2025
4307549
Remove CompatibilitySuppressions.xml
jonathandavies-arm May 20, 2025
ad1aa4c
Merge branch 'main' into upstream/sve/rename-prefetch-apis
jonathandavies-arm May 20, 2025
fc9e072
Merge branch 'main' into upstream/sve/rename-prefetch-apis
jonathandavies-arm May 29, 2025
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8 changes: 4 additions & 4 deletions src/coreclr/jit/fgdiagnostic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3458,10 +3458,10 @@ void Compiler::fgDebugCheckFlags(GenTree* tree, BasicBlock* block)
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_GatherPrefetch8Bit:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_GetFfrByte:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/jit/gentree.cpp
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Expand Up @@ -28698,10 +28698,6 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const

#if defined(TARGET_ARM64)
case NI_ArmBase_Yield:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_GatherPrefetch16Bit:
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
Expand All @@ -28714,6 +28710,10 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const
case NI_Sve_GetFfrUInt16:
case NI_Sve_GetFfrUInt32:
case NI_Sve_GetFfrUInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_SetFfr:
{
return true;
Expand Down Expand Up @@ -28916,10 +28916,10 @@ void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_GatherPrefetch8Bit:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_GetFfrByte:
case NI_Sve_GetFfrInt16:
case NI_Sve_GetFfrInt32:
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -508,10 +508,10 @@ void HWIntrinsicInfo::lookupImmBounds(
case NI_Sve_GatherPrefetch16Bit:
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
immLowerBound = (int)SVE_PRFOP_PLDL1KEEP;
immUpperBound = (int)SVE_PRFOP_CONST15;
break;
Expand Down Expand Up @@ -3182,10 +3182,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
case NI_Sve_GatherPrefetch16Bit:
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
{
assert((sig->numArgs == 3) || (sig->numArgs == 4));
assert(!isScalar);
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/hwintrinsiccodegenarm64.cpp
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Expand Up @@ -1786,10 +1786,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
{
assert(hasImmediateOperand);
HWIntrinsicImmOpHelper helper(this, intrin.op3, node);
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/hwintrinsiclistarm64sve.h
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Expand Up @@ -227,10 +227,10 @@ HARDWARE_INTRINSIC(Sve, Not,
HARDWARE_INTRINSIC(Sve, Or, -1, -1, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant)
HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ReduceOperation)
HARDWARE_INTRINSIC(Sve, PopCount, -1, -1, {INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, PrefetchBytes, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, PrefetchInt16, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, PrefetchInt32, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, PrefetchInt64, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, Prefetch16Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, Prefetch32Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, Prefetch64Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, Prefetch8Bit, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other)
HARDWARE_INTRINSIC(Sve, ReciprocalEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpe, INS_sve_frecpe}, HW_Category_SIMD, HW_Flag_Scalable)
HARDWARE_INTRINSIC(Sve, ReciprocalExponent, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpx, INS_sve_frecpx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation)
HARDWARE_INTRINSIC(Sve, ReciprocalSqrtEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frsqrte, INS_sve_frsqrte}, HW_Category_SIMD, HW_Flag_Scalable)
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/lowerarmarch.cpp
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Expand Up @@ -3820,10 +3820,10 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_StoreSelectedScalar:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_ExtractVector:
case NI_Sve_AddRotateComplex:
case NI_Sve_TrigonometricMultiplyAddCoefficient:
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/jit/lsraarm64.cpp
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Expand Up @@ -1655,10 +1655,10 @@ void LinearScan::BuildHWIntrinsicImmediate(GenTreeHWIntrinsic* intrinsicTree, co
case NI_AdvSimd_ExtractVector128:
case NI_AdvSimd_StoreSelectedScalar:
case NI_AdvSimd_Arm64_StoreSelectedScalar:
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
case NI_Sve_ExtractVector:
case NI_Sve_TrigonometricMultiplyAddCoefficient:
needBranchTargetReg = !intrin.op3->isContainedIntOrIImmed();
Expand Down Expand Up @@ -2356,14 +2356,14 @@ GenTree* LinearScan::getVectorAddrOperand(GenTreeHWIntrinsic* intrinsicTree)
// Operands that are not loads or stores but do require an address
switch (intrinsicTree->GetHWIntrinsicId())
{
case NI_Sve_PrefetchBytes:
case NI_Sve_PrefetchInt16:
case NI_Sve_PrefetchInt32:
case NI_Sve_PrefetchInt64:
case NI_Sve_GatherPrefetch8Bit:
case NI_Sve_GatherPrefetch16Bit:
case NI_Sve_GatherPrefetch32Bit:
case NI_Sve_GatherPrefetch64Bit:
case NI_Sve_Prefetch16Bit:
case NI_Sve_Prefetch32Bit:
case NI_Sve_Prefetch64Bit:
case NI_Sve_Prefetch8Bit:
if (!varTypeIsSIMD(intrinsicTree->Op(2)->gtType))
{
return intrinsicTree->Op(2);
Expand Down
24 changes: 12 additions & 12 deletions ...ries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs
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Expand Up @@ -7422,22 +7422,13 @@ internal Arm64() { }
public static Vector<ulong> PopCount(Vector<ulong> value) { throw new PlatformNotSupportedException(); }


// Prefetch bytes

/// <summary>
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchBytes(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }


// Prefetch halfwords

/// <summary>
/// <para>void svprfh(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFH op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt16(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
public static unsafe void Prefetch16Bit(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }


// Prefetch words
Expand All @@ -7446,7 +7437,7 @@ internal Arm64() { }
/// <para>void svprfw(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFW op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt32(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
public static unsafe void Prefetch32Bit(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }


// Prefetch doublewords
Expand All @@ -7455,7 +7446,16 @@ internal Arm64() { }
/// <para>void svprfd(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFD op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt64(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }
public static unsafe void Prefetch64Bit(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }


// Prefetch bytes

/// <summary>
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void Prefetch8Bit(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); }


// Reciprocal estimate
Expand Down
24 changes: 12 additions & 12 deletions src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs
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Expand Up @@ -7413,22 +7413,13 @@ internal Arm64() { }
public static Vector<ulong> PopCount(Vector<ulong> value) => PopCount(value);


// Prefetch bytes

/// <summary>
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchBytes(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchBytes(mask, address, prefetchType);


// Prefetch halfwords

/// <summary>
/// <para>void svprfh(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFH op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt16(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt16(mask, address, prefetchType);
public static unsafe void Prefetch16Bit(Vector<ushort> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch16Bit(mask, address, prefetchType);


// Prefetch words
Expand All @@ -7437,7 +7428,7 @@ internal Arm64() { }
/// <para>void svprfw(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFW op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt32(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt32(mask, address, prefetchType);
public static unsafe void Prefetch32Bit(Vector<uint> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch32Bit(mask, address, prefetchType);


// Prefetch doublewords
Expand All @@ -7446,7 +7437,16 @@ internal Arm64() { }
/// <para>void svprfd(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFD op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void PrefetchInt64(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt64(mask, address, prefetchType);
public static unsafe void Prefetch64Bit(Vector<ulong> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch64Bit(mask, address, prefetchType);


// Prefetch bytes

/// <summary>
/// <para>void svprfb(svbool_t pg, const void *base, enum svprfop op)</para>
/// <para> PRFB op, Pg, [Xbase, #0, MUL VL]</para>
/// </summary>
public static unsafe void Prefetch8Bit(Vector<byte> mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch8Bit(mask, address, prefetchType);


// Reciprocal estimate
Expand Down
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