JIT: Support bitwise field insertions for call arguments #115977
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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@@ -1725,20 +1725,12 @@ void Lowering::LowerArg(GenTreeCall* call, CallArg* callArg) | |
| { | ||
| if (abiInfo.HasAnyRegisterSegment()) | ||
| { | ||
| if (arg->OperIs(GT_FIELD_LIST)) | ||
| { | ||
| LowerArgFieldList(callArg, arg->AsFieldList()); | ||
| arg = *ppArg; | ||
|
There was a problem hiding this comment. This is enabled everywhere now since even single-reg args can be structs with multiple fields. |
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| } | ||
| else | ||
| { | ||
| assert(abiInfo.HasExactlyOneRegisterSegment()); | ||
| InsertPutArgReg(ppArg, abiInfo.Segment(0)); | ||
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@@ -4809,6 +4801,18 @@ void Lowering::LowerRet(GenTreeOp* ret) | |
| ContainCheckRet(ret); | ||
| } | ||
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| struct LowerFieldListRegisterInfo | ||
| { | ||
| unsigned Offset; | ||
| var_types RegType; | ||
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| LowerFieldListRegisterInfo(unsigned offset, var_types regType) | ||
| : Offset(offset) | ||
| , RegType(regType) | ||
| { | ||
| } | ||
| }; | ||
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||
| //---------------------------------------------------------------------------------------------- | ||
| // LowerRetFieldList: | ||
| // Lower a returned FIELD_LIST node. | ||
|
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@@ -4822,21 +4826,18 @@ void Lowering::LowerRetFieldList(GenTreeOp* ret, GenTreeFieldList* fieldList) | |
| const ReturnTypeDesc& retDesc = comp->compRetTypeDesc; | ||
| unsigned numRegs = retDesc.GetReturnRegCount(); | ||
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| auto getRegInfo = [=, &retDesc](unsigned regIndex) { | ||
| unsigned offset = retDesc.GetReturnFieldOffset(regIndex); | ||
| var_types regType = genActualType(retDesc.GetReturnRegType(regIndex)); | ||
| return LowerFieldListRegisterInfo(offset, regType); | ||
| }; | ||
|
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| bool isCompatible = IsFieldListCompatibleWithRegisters(fieldList, numRegs, getRegInfo); | ||
| if (!isCompatible) | ||
| { | ||
| unsigned lclNum = | ||
| StoreFieldListToNewLocal(comp->typGetObjLayout(comp->info.compMethodInfo->args.retTypeClass), fieldList); | ||
| LclVarDsc* varDsc = comp->lvaGetDesc(lclNum); | ||
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| GenTree* retValue = comp->gtNewLclvNode(lclNum, varDsc->TypeGet()); | ||
| ret->SetReturnValue(retValue); | ||
|
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@@ -4859,7 +4860,89 @@ void Lowering::LowerRetFieldList(GenTreeOp* ret, GenTreeFieldList* fieldList) | |
| return; | ||
| } | ||
|
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| LowerFieldListToFieldListOfRegisters(fieldList, numRegs, getRegInfo); | ||
| } | ||
|
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| //---------------------------------------------------------------------------------------------- | ||
| // StoreFieldListToNewLocal: | ||
| // Create a new local with the specified layout and store the specified | ||
| // fields of the specified FIELD_LIST into it. | ||
| // | ||
| // Arguments: | ||
| // layout - Layout of the new local | ||
| // fieldList - Fields to store to it | ||
| // | ||
| // Returns: | ||
| // Var number of new local. | ||
| // | ||
| unsigned Lowering::StoreFieldListToNewLocal(ClassLayout* layout, GenTreeFieldList* fieldList) | ||
| { | ||
| JITDUMP("Spilling field list [%06u] to stack\n", Compiler::dspTreeID(fieldList)); | ||
| unsigned lclNum = comp->lvaGrabTemp(true DEBUGARG("Spilled local for field list")); | ||
| LclVarDsc* varDsc = comp->lvaGetDesc(lclNum); | ||
| comp->lvaSetStruct(lclNum, layout, false); | ||
| comp->lvaSetVarDoNotEnregister(lclNum DEBUGARG(DoNotEnregisterReason::LocalField)); | ||
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| for (GenTreeFieldList::Use& use : fieldList->Uses()) | ||
| { | ||
| GenTree* store = comp->gtNewStoreLclFldNode(lclNum, use.GetType(), use.GetOffset(), use.GetNode()); | ||
| BlockRange().InsertAfter(use.GetNode(), store); | ||
| LowerNode(store); | ||
| } | ||
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| return lclNum; | ||
| } | ||
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| //---------------------------------------------------------------------------------------------- | ||
| // LowerArgFieldList: | ||
| // Lower an argument FIELD_LIST node. | ||
| // | ||
| // Arguments: | ||
| // arg - The argument | ||
| // fieldList - The FIELD_LIST node | ||
| // | ||
| void Lowering::LowerArgFieldList(CallArg* arg, GenTreeFieldList* fieldList) | ||
| { | ||
| assert(!arg->AbiInfo.HasAnyStackSegment()); | ||
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| auto getRegInfo = [=](unsigned regIndex) { | ||
| const ABIPassingSegment& seg = arg->AbiInfo.Segment(regIndex); | ||
| return LowerFieldListRegisterInfo(seg.Offset, seg.GetRegisterType()); | ||
| }; | ||
|
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| bool isCompatible = IsFieldListCompatibleWithRegisters(fieldList, arg->AbiInfo.NumSegments, getRegInfo); | ||
| if (!isCompatible) | ||
| { | ||
| ClassLayout* layout = comp->typGetObjLayout(arg->GetSignatureClassHandle()); | ||
| unsigned lclNum = StoreFieldListToNewLocal(layout, fieldList); | ||
| fieldList->Uses().Clear(); | ||
| for (const ABIPassingSegment& seg : arg->AbiInfo.Segments()) | ||
| { | ||
| GenTreeLclFld* fld = comp->gtNewLclFldNode(lclNum, seg.GetRegisterType(layout), seg.Offset); | ||
| fieldList->AddFieldLIR(comp, fld, seg.Offset, fld->TypeGet()); | ||
| BlockRange().InsertBefore(fieldList, fld); | ||
| } | ||
| } | ||
| else | ||
| { | ||
| LowerFieldListToFieldListOfRegisters(fieldList, arg->AbiInfo.NumSegments, getRegInfo); | ||
| } | ||
|
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| GenTreeFieldList::Use* field = fieldList->Uses().GetHead(); | ||
| for (const ABIPassingSegment& seg : arg->AbiInfo.Segments()) | ||
| { | ||
| assert((field != nullptr) && "Ran out of fields while inserting PUTARG_REG"); | ||
| InsertPutArgReg(&field->NodeRef(), seg); | ||
| field = field->GetNext(); | ||
| } | ||
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| assert((field == nullptr) && "Missed fields while inserting PUTARG_REG"); | ||
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| arg->NodeRef() = fieldList->SoleFieldOrThis(); | ||
| if (arg->GetNode() != fieldList) | ||
| { | ||
| BlockRange().Remove(fieldList); | ||
| } | ||
| } | ||
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| //---------------------------------------------------------------------------------------------- | ||
|
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@@ -4874,21 +4957,29 @@ void Lowering::LowerRetFieldList(GenTreeOp* ret, GenTreeFieldList* fieldList) | |
| // True if the fields of the FIELD_LIST are all direct insertions into the | ||
| // return registers. | ||
| // | ||
| template <typename GetRegisterInfoFunc> | ||
| bool Lowering::IsFieldListCompatibleWithRegisters(GenTreeFieldList* fieldList, | ||
| unsigned numRegs, | ||
| GetRegisterInfoFunc getRegInfo) | ||
| { | ||
| JITDUMP("Checking if field list [%06u] is compatible with registers: ", Compiler::dspTreeID(fieldList)); | ||
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| GenTreeFieldList::Use* use = fieldList->Uses().GetHead(); | ||
| for (unsigned i = 0; i < numRegs; i++) | ||
| { | ||
| LowerFieldListRegisterInfo regInfo = getRegInfo(i); | ||
| unsigned regStart = regInfo.Offset; | ||
| var_types regType = regInfo.RegType; | ||
| unsigned regEnd = regStart + genTypeSize(regType); | ||
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| if ((i == numRegs - 1) && !varTypeUsesFloatReg(regType)) | ||
| { | ||
| // Allow tail end to pass undefined bits into the register | ||
| regEnd = regStart + REGSIZE_BYTES; | ||
|
There was a problem hiding this comment. I'm just curious, do we have a guarantee that we won't load the undefined bits as a payload somehow? There was a problem hiding this comment. Yes, upper bits of registers containing struct values are undefined in the managed ABI. So this is ok. (This is just ensuring the handling matches what we had before; without this there was a bunch of regressions). I think the actual source that creates these loads is morph: runtime/src/coreclr/jit/morph.cpp Lines 2442 to 2449 in 7e41ae6 I'm not sure it's worth it -- this means we sometimes can generate 2x 8byte loads => ldp instead of one 8 byte + one < 8 byte load, so the code is slightly smaller. But then maybe that may result in a stall? Probably worth to see if we can come up with an example and then maybe remove it if we can. |
||
| } | ||
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| // TODO-CQ: Could just create a 0 for this. | ||
| if ((use == nullptr) || (use->GetOffset() >= regEnd)) | ||
| { | ||
| JITDUMP("it is not; register %u has no corresponding field\n", i); | ||
| return false; | ||
|
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@@ -4949,19 +5040,26 @@ bool Lowering::IsFieldListCompatibleWithReturn(GenTreeFieldList* fieldList) | |
| // Arguments: | ||
| // fieldList - The field list | ||
| // | ||
| template <typename GetRegisterInfoFunc> | ||
| void Lowering::LowerFieldListToFieldListOfRegisters(GenTreeFieldList* fieldList, | ||
| unsigned numRegs, | ||
| GetRegisterInfoFunc getRegInfo) | ||
| { | ||
| GenTreeFieldList::Use* use = fieldList->Uses().GetHead(); | ||
| assert(fieldList->Uses().IsSorted()); | ||
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| for (unsigned i = 0; i < numRegs; i++) | ||
| { | ||
| LowerFieldListRegisterInfo regInfo = getRegInfo(i); | ||
| unsigned regStart = regInfo.Offset; | ||
| var_types regType = regInfo.RegType; | ||
| unsigned regEnd = regStart + genTypeSize(regType); | ||
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| if ((i == numRegs - 1) && !varTypeUsesFloatReg(regType)) | ||
| { | ||
| // Allow tail end to pass undefined bits into the register | ||
| regEnd = regStart + REGSIZE_BYTES; | ||
| } | ||
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| GenTreeFieldList::Use* regEntry = use; | ||
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@@ -5001,7 +5099,7 @@ void Lowering::LowerFieldListToFieldListOfRegisters(GenTreeFieldList* fieldList) | |
| } | ||
|
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| // If this is a float -> int insertion, then we need the bitcast now. | ||
| if (varTypeUsesFloatReg(value) && varTypeUsesIntReg(regInfo.RegType)) | ||
| { | ||
| assert((genTypeSize(value) == 4) || (genTypeSize(value) == 8)); | ||
| var_types castType = genTypeSize(value) == 4 ? TYP_INT : TYP_LONG; | ||
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nit: the formatting is a bit off (2 spaces vs 3 spaces for Return value, also, missing arg section)
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Let me address that in a follow-up