Run ULP-fsm on XTAL 20MHz - ESP32S3 (IDFGH-16893)

[patryk-belka-wizzdev]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

General issue report

Hi,
Since the 17.5Mhz RTC-fast clock on the ESP32-S3 is very unstable (I measured over 160kHz fluctuations) and different on each chip (from 16Mhz to 19Mhz) i wanted to run my code on the stable 20MHz Xtal-d2.
I set the XTAL as source for RTC-fast clock with:
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, 0);
and
ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON));
to keep the XTAL powered
and it works for the ULP in normal mode, but when the esp enters deep-sleep, the ULP switches to ~150Khz, which seems to be the RTC_SLOW clock.
Is there a way to keep the 20MHz XTAL as source for the ULP in deep-sleep?

[alhyene]

For my part I think deep-sleep mean what it mean. XTAL drivers are energy consumers. Then it make sense it switch to the ~150Khz one.
Why not try to calibrate the RTC-fast clock. You could read chip temperature and measure volltage then have a sort of matrix...

[alhyene]

I forgot what you want to do in deep sleep apart waiting for something ?

[patryk-belka-wizzdev]

In my application, the ULP needs to run at a steady clock all the time, no matter what the ESP main CPU is doing. The ULP is decoding radio input and is timed to work with the radio protocol baud rate. I noticed that the RTC-fast clock speed is getting lower with the temperature of the chip. That means in my case, after waking up from deepsleep frequency was about 18.27Mhz, dropping to 18.1MHz in few minutes of the ESP running. Thats about 159.7kHz peak-to-peak fluctuation with ~45kHz standard deviation. When blowing hot-air (~90*C) on the chip, the clock speed went down to less than 1.78 in a few seconds (a 447.5KHz fall!!).
Since my ULP application is quite time-deterministic, running quite independently of the ESP, i need to find a more stable clock source.
I thought that the esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); would keep the XTAL powered in deep-sleep. Otherwise, I don't understand what this option is for.

[alhyene]

I think with esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); you shut down XTAL power...

May be this could help...
https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/system/sleep_modes.html

But I agree there's could some "little drifts" with temperature and voltage...
:*)

[alhyene]

In ULP you could do a serial connection not much more than 9600 bauds stable... 19200 ?
You want to have a 3 cores processor ?
;*)

[patryk-belka-wizzdev]

The ESP_PD_OPTION_ON explicitly says: "Keep power domain enabled during sleep mode."
All I need is the ULP to have a stable GPIO read every 488us (4 samples per bit in 512 baudrate), while the ESP is most time in deep sleep. Low power consumption is quite important; thus, deep sleep is preferred over light sleep.

[alhyene]

I wish to understand your problems maybe you don't look welll at the specs.
Minut butetrfly I've got a fly... away...
Hope you gonna througt and help the community.
Sincerly, Dd.