@@ -114,9 +114,11 @@ def write_project_cpp(self, model):
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## myproject.cpp
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###################
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+ project_name = model .config .get_project_name ()
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+
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filedir = os .path .dirname (os .path .abspath (__file__ ))
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f = open (os .path .join (filedir , '../templates/quartus/firmware/myproject.cpp' ), 'r' )
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- fout = open ('{}/firmware/{}.cpp' .format (model .config .get_output_dir (), model . config . get_project_name () ), 'w' )
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+ fout = open ('{}/firmware/{}.cpp' .format (model .config .get_output_dir (), project_name ), 'w' )
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model_inputs = model .get_input_variables ()
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model_outputs = model .get_output_variables ()
@@ -127,7 +129,7 @@ def write_project_cpp(self, model):
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for line in f .readlines ():
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# Add headers to weights and biases
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if 'myproject' in line :
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- newline = line .replace ('myproject' , model . config . get_project_name () )
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+ newline = line .replace ('myproject' , project_name )
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# Intel HLS 'streams' need to be passed by reference to top-level entity or declared as global variables
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# Streams cannot be declared inside a function
@@ -146,29 +148,29 @@ def write_project_cpp(self, model):
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elif '//hls-fpga-machine-learning instantiate GCC top-level' in line :
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newline = line
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if io_type == 'io_stream' :
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- newline += 'void myproject (\n '
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+ newline += f 'void { project_name } (\n '
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for inp in model_inputs :
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newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
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for out in model_outputs :
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newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
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newline += ') {\n '
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if io_type == 'io_parallel' :
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- newline = 'output_data myproject (\n '
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+ newline = f 'output_data { project_name } (\n '
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newline += indent + 'input_data inputs\n '
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newline += ') {\n '
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# Instantiate HLS top-level function, to be used during HLS synthesis
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elif '//hls-fpga-machine-learning instantiate HLS top-level' in line :
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newline = line
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if io_type == 'io_stream' :
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- newline += 'component void myproject (\n '
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+ newline += f 'component void { project_name } (\n '
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for inp in model_inputs :
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newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
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for out in model_outputs :
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newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
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newline += ') {\n '
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if io_type == 'io_parallel' :
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- newline += 'component output_data myproject (\n '
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+ newline += f 'component output_data { project_name } (\n '
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newline += indent + 'input_data inputs\n '
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newline += ') {\n '
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@@ -263,9 +265,11 @@ def write_project_header(self, model):
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## myproject.h
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#######################
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+ project_name = model .config .get_project_name ()
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+
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filedir = os .path .dirname (os .path .abspath (__file__ ))
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f = open (os .path .join (filedir , '../templates/quartus/firmware/myproject.h' ), 'r' )
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- fout = open ('{}/firmware/{}.h' .format (model .config .get_output_dir (), model . config . get_project_name () ), 'w' )
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+ fout = open ('{}/firmware/{}.h' .format (model .config .get_output_dir (), project_name ), 'w' )
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model_inputs = model .get_input_variables ()
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model_outputs = model .get_output_variables ()
@@ -276,39 +280,40 @@ def write_project_header(self, model):
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for line in f .readlines ():
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if 'MYPROJECT' in line :
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- newline = line .replace ('MYPROJECT' , format (model . config . get_project_name () .upper ()))
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+ newline = line .replace ('MYPROJECT' , format (project_name .upper ()))
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elif 'myproject' in line :
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- newline = line .replace ('myproject' , model . config . get_project_name () )
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+ newline = line .replace ('myproject' , project_name )
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elif '//hls-fpga-machine-learning instantiate GCC top-level' in line :
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newline = line
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# For io_stream, input and output are passed by reference; see myproject.h & myproject.cpp for more details
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+
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if io_type == 'io_stream' :
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- newline += 'void myproject (\n '
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+ newline += f 'void { project_name } (\n '
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for inp in model_inputs :
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newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
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for out in model_outputs :
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newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
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newline += ');\n '
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# In io_parallel, a struct is returned; see myproject.h & myproject.cpp for more details
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else :
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- newline += 'output_data myproject (\n '
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+ newline += f 'output_data { project_name } (\n '
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newline += indent + 'input_data inputs\n '
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newline += ');\n '
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# Similar to GCC instantiation, but with the keyword 'component'
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elif '//hls-fpga-machine-learning instantiate HLS top-level' in line :
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newline = line
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if io_type == 'io_stream' :
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- newline += 'component void myproject (\n '
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+ newline += f 'component void { project_name } (\n '
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for inp in model_inputs :
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newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
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for out in model_outputs :
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newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
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newline += ');\n '
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else :
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- newline += 'component output_data myproject (\n '
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+ newline += f 'component output_data { project_name } (\n '
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newline += indent + 'input_data inputs\n '
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newline += ');\n '
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