Alveo-Pynq implementation

[Gabriele-bot]

Hello,

in the last couple of months I've been working with the hls4ml framework and the PYNQ implementation is just simple and easy to use.
I decided to work on Alveo-Pynq implementation exploiting Vitis to produce a .xclbin file that contains the hls4ml IP with axi_stream interface.

I followed the instructions provided by Xilinx at this link and I've come up with somewhat of an automated procedure to do the same mimicking the work done on the Pynq-z2 board.
I forked the release 0.6.0 and add my codes, the specific branch can be found here.
I did not run any test of the /test section yet, but I run some code in this repository to evaluate the overall stability.

If I wish to contribute which test should I run/produce?

Thanks

[thesps]

Hi, thanks a lot for this, we're taking a look at what you've implemented. I have a question for you: what's the purpose of the Verilog modules? Are they to convert the AXI Stream that the HLS IP expects to AXI master? Is that something we could do at the HLS level instead? i.e. apply pragmas for AXI Master interface rather than AXI Stream.

[Gabriele-bot]

The Verilog modules are, as you said, a sort of wrapper to convert AXIS to AXI-Master it is like the DMA in the PYNQ-Z2 implementation; in fact the Alveo kernel need one and only one AXI-Lite interface (control purposes) and none/one/multiple AXI-Master interface/s (data movement).
I'm kind of an hardware guy so I'm not familiar with HLS (but I'm planning to add it to my knowledge), so I don't know if it possible to jump directly to kernel compilation directly from Vivado HLS; on top of that many of the examples that produce the Alveo kernel invoke VITIS HLS, so maybe the kernel can be compiled and linked directly on the C/C++ level, but I did not look too much in depth.

I hope to have cleared some of your doubts. If you have any other questions, just ask I will more than happy to reply.