Fixed sign parsing for ac_fixed and ac_int

hls4ml/backends/fpga/fpga_backend.py

@@ -342,14 +342,20 @@ def _convert_ac_type(cls, precision):
             integer = int(bits[1])
             fields = 2
             if len(bits) > 2:
-                signed = bool(bits[2])
+                # only if the third argument is false or 0, set signed to False
+                # (default is True)
+                if bits[2].strip().lower() in ['false', '0']:
+                    signed = False
                 fields = 3
         elif 'int' in precision:
             width = int(bits[0])
             integer = width
             fields = 1
             if len(bits) > 1:
-                signed = bool(bits[1])
+                # only if the second argument is false or 0, set signed to False
+                # (default is True)
+                if bits[1].strip().lower() in ['false', '0']:
+                    signed = False
                 fields = 2
         if len(bits) > fields:
             round_mode = bits[fields]

test/pytest/test_precision_parsing.py

@@ -0,0 +1,29 @@
+import pytest
+
+import hls4ml
+
+
+@pytest.mark.parametrize(
+    'prec_pair',
+    [
+        ('ap_fixed<3, 2>', True),
+        ('ap_ufixed<3, 2>', False),
+        ('ac_fixed<3, 2, true>', True),
+        ('ac_fixed<3, 2, false>', False),
+        ('ac_fixed<3, 2, 1>', True),
+        ('ac_fixed<3, 2, 0>', False),
+        ('ap_int<3, 2>', True),
+        ('ap_uint<3>', False),
+        ('ac_int<3, TRue>', True),
+        ('ac_int<3, FALse>', False),
+        ('ac_int<3, 1>', True),
+        ('ac_int<3, 0>', False),
+    ],
+)
+def test_sign_parsing(prec_pair):
+    '''Test that convert_precions_string determines the signedness correctly'''
+    strprec = prec_pair[0]
+    signed = prec_pair[1]
+
+    evalprec = hls4ml.backends.fpga.fpga_backend.FPGABackend.convert_precision_string(strprec)
+    assert evalprec.signed == signed