CUDA: fix logic for V100 + GGML_CUDA_FORCE_MMQ #12098
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Fixes LostRuins#1390 .
The logic for the combination of V100s and
GGML_CUDA_FORCE_MMQseems to be wrong on master. By default, when compiling withoutGGML_CUDA_FORCE_MMQ, the MMQ kernels should only be compiled for batch sizes up toMMQ_DP4A_MAX_BATCH_SIZEif FP16 tensor core hardware is available but int8 tensor core hardware is not (basically only V100s). Template specializations for higher batch sizes will never be used. However, the condition for this seems to have been inverted. WithoutGGML_CUDA_FORCE_MMQunneeded template specializations were being compiled and with it the host code could attempt to run nonexistent kernels.