LVS issues

[martinjankoehler]

Test suite for cells

• Test suite
  • test each PCell in isolation (only labels for pins)
  • Cells
    • cmim_eval.gds
    • hbt_eval.gds (see Issue 2 below)
    • nmos_eval.gds
    • nmos_eval_sub.gds
    • pmos_eval.gds
    • pmos_eval_sub.gds
    • rppd_eval.gds
      • PR pending: https://github.com/IHP-GmbH/IHP-Open-PDK/pull/669/files
    • All Resistors: changing bulk connection should be detectable with LVS (see Issue 6 below)
    • rfcmim_eval.gds (see Issue 7 below)
    • rfnmos
    • nmos_dnw / isolbox (see Issue 9 below)

Issue 2

• Cell hbt_eval.gds
  • changing pin vss to vss1 should trigger an error
    • the cmd line logs an error
    • the Log tab shows an error
    • but no markers are generated pointing to the wrong port pin
• GDS/SPICE: hbt_eval.zip

Issue 3 (nmos)

• LVS Mismatch: Netlist browser is not helping when a polarity in the schematic for the symbol ptap is reversed
• EDIT: won't fix, this is due to KLayout backtracking algorithm (no low hanging fruits there)

Issue 4 (nmos with sub!)

• if sub! is removed from the schematic, it works
• but sub! should be part of the schematic

Issue 5 (pmos)

• works without extra guard ring (for sub)
• with extra guard ring fails (same as Issue 4)

Issue 6 (Resistor Bulk connection)

• normally, the bulk pin is sub!
• but if the bulk pin is changed to somethingelse, this does not get recognized by LVS, because lvsformat of the Symbol gets thrown away (no body=@body is passed in lvsformat). This is because historically:
  • orginally, resistors were 2-pin
  • now, symbols are 3-pin
  • but the LVS device detection script does not support 3-pin yet, only 2-pin

Issue 7 (rfcmim)

• Symbol cap_rfcmim.sym
  • pcell and symbol (w / l / wfeed) should be the same by default, so the symbol should be changed:
    • w=7.0e-6
    • l=7.0e-6
    • wfeed=3.0e-6
  • lvsformat is missing at all

K {type=capacitor
lvs_format="@name @pinlist @model w=@w l=@l m=@m"
format="@spiceprefix@name @pinlist @model w=@w l=@l wfeed=@wfeed"
template="name=C1 
model=cap_rfcmim
w=7.0e-6
l=7.0e-6
wfeed=3.0e-6
spiceprefix=X"
drc="mim_drc @name @symname @model @w @l"

• extraction rule set for cap_extraction.lvs ... name is wrong (is rfcmim, cap_rfcmim)

Issue 8 (rfnmos)

• Mismatch
  • Extraction script rfmos_extraction.lvs defines rfnmos
  • LVS expects SG13_LV_NMOS

Issue 9 (nmos_dnw) / isolbox

• how to create LVS-clean deep nwell, e.g. by combining nmos/isolbox/ptab?
• do meeting with IHP and @p-fath and @hpretl