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ssarangi opened this issue Feb 2, 2018 · 0 comments
Closed

Formatting is off for the following lines. #2

ssarangi opened this issue Feb 2, 2018 · 0 comments

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@ssarangi
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ssarangi commented Feb 2, 2018 •
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intel-graphics-compiler/IGC/Compiler/Optimizer/BuiltInFuncImport.cpp

Line 571 in 582b5ab

float profilingTimerResolution = static_cast<OpenCLProgramContext*>(pCtx)->getProfilingTimerResolution();

intel-graphics-compiler/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

Line 373 in 582b5ab

m_currShader->SetPushInfoHelper(&(m_moduleMD->pushInfo));

@ssarangi ssarangi changed the title Formatting seems to be off for this commit. Formatting is off for the following lines. Feb 2, 2018
VPG-SWE-Github pushed a commit that referenced this issue Nov 2, 2020
@igcbot @jwarumze
Changes in code. (#2)
935b24d 
Co-authored-by: Warumzer, Jakub <[email protected]>
VPG-SWE-Github pushed a commit that referenced this issue Nov 3, 2020
@igcbot @jwarumze
Changes in code. (#2)
b397e06 
Co-authored-by: Warumzer, Jakub <[email protected]>
VPG-SWE-Github pushed a commit that referenced this issue Nov 3, 2020
@jwarumze
Changes in code. (#2)
a85b828
VPG-SWE-Github pushed a commit that referenced this issue Nov 3, 2020
@jwarumze @igcbot
Changes in code. (#2)
e21e39f
VPG-SWE-Github pushed a commit that referenced this issue Nov 3, 2020
@jwarumze @igcbot
Changes in code. (#2)
a655df0
VPG-SWE-Github pushed a commit that referenced this issue Nov 5, 2020
@jwarumze @igcbot
Changes in code. (#2)
9b60058
VPG-SWE-Github pushed a commit that referenced this issue Apr 20, 2021
@trbauer @igcbot
High-Level Load/Store G4IR support.
21ad6a9 
The goal is to move us away from twiddling bits in descriptors every time we need to examine or modify send messages.
* All send descriptors (formerly G4_SendMsgDescriptor) are subclasses of G4_SendDesc
* The old raw descriptor is G4_SendDescRaw and there is a new G4_SendDescLdSt which is unused at the moment.
* Anywhere possible, we now use the generic methods of the superclass G4_SendDesc.
* In cases where the old code fiddles with bits directly and requires the raw descriptor, we add a type check and convert to G4_SendDescRaw (assert on fail / return false on pattern match if safe to do so (e.g. SendFusion::canFuse(..))).
* Do not let the old raw descriptor gunk pollute the generic interface of the parent.
* retry #2 of reverted ci-comp_igc-10352/#19876 (fixed defect with G4_InstSend::canBeEot())
VPG-SWE-Github pushed a commit that referenced this issue Jun 29, 2021
@dlei6g @igcbot
* Add BE support for struct arg and return codegen. This is a redesig…
507f71d 
…n of the small struct passing optimization for stackcalls.

The previous commit converts struct pointer args into integer data values, however with this method we must use bitwise extraction to get individual struct elements.
The struct arguments, when passed as integers, are stored as AoS format in registers, and we must do a lot of shuffling in the BE to extract all lanes of each element.

This change adds BE support to handle vISA code emission for struct type values. Structs are represented as a vector of BYTES, and are stored as SoA format in registers.
The IGC FE transforms small struct pointers with the "byval" or "sret" attributes back to pass-by-value, and thus selectively undos the SPIRV FE transformation.
Small struct args and retvals are handled directly by vISA codegen in the BE, while larger structs remains pass-by-pointer. Promotable struct sizes can be tuned to minimize spill.

* Commit attempt #2 - Fixed struct load/store
VPG-SWE-Github pushed a commit that referenced this issue Aug 27, 2021
@fangliu2020 @igcbot
Enable ForcePrivateMemoryToGlobalOnGeneric and DetectCastToGAS optio…
ddc2fa3 
…ns by default. #2 try.

These two options are used to enable omission of private/local address space checks
for generic pointer load/store.
VPG-SWE-Github pushed a commit that referenced this issue Aug 27, 2021
@fangliu2020 @igcbot
Enable madw use in i64 mul emulator. #2 try.
d34d0af 
Fixed the regression caused by a regioning issue in moving madw low/high results
to other variables. And enable madw use in i64 mul emulator again.
befor fix:
madw (M1_NM, 1) int64Tmp(0,0)<1> localSize_0(0,0)<0;1,0> localSize_0(0,1)<0;1,0> 0x0:ud
mov (M1_NM, 1) V0101(0,0)<1> int64Tmp(0,0)<1;1,0>
mov (M1_NM, 1) V0103(0,0)<1> int64Tmp(2,0)<1;1,0>
After fix:
madw (M1_NM, 1) int64Tmp(0,0)<1> localSize_0(0,0)<0;1,0> localSize_0(0,1)<0;1,0> 0x0:ud
mov (M1_NM, 1) V0101(0,0)<1> int64Tmp(0,0)<1;1,0>
mov (M1_NM, 1) V0103(0,0)<1> int64Tmp(1,0)<1;1,0>
VPG-SWE-Github pushed a commit that referenced this issue Aug 29, 2021
@fangliu2020 @igcbot
[Autobackout][FuncReg]Revert of change: d34d0af
7c19248 
 Enable madw use in i64 mul emulator. #2 try.

Fixed the regression caused by a regioning issue in moving madw low/high results
to other variables. And enable madw use in i64 mul emulator again.
befor fix:
madw (M1_NM, 1) int64Tmp(0,0)<1> localSize_0(0,0)<0;1,0> localSize_0(0,1)<0;1,0> 0x0:ud
mov (M1_NM, 1) V0101(0,0)<1> int64Tmp(0,0)<1;1,0>
mov (M1_NM, 1) V0103(0,0)<1> int64Tmp(2,0)<1;1,0>
After fix:
madw (M1_NM, 1) int64Tmp(0,0)<1> localSize_0(0,0)<0;1,0> localSize_0(0,1)<0;1,0> 0x0:ud
mov (M1_NM, 1) V0101(0,0)<1> int64Tmp(0,0)<1;1,0>
mov (M1_NM, 1) V0103(0,0)<1> int64Tmp(1,0)<1;1,0>
VPG-SWE-Github pushed a commit that referenced this issue Sep 25, 2021
@fangliu2020 @igcbot
[vISA]: Fix the WAW/WAR issue of ACC caused by mul/mulh/madw in loca…
69a5cbd 
…l scheduling. #2 try.

on some platforms, mul/mulh/madw will be expanded into mul+mach/macl after local scheduling.
Since ACC is used as dst of expanded mul, it is a must to set implicit ACC as dst
of mul/mulh/madw. Otherwise, there will be WAW/WAR issue of ACC in local scheduling.
VPG-SWE-Github pushed a commit that referenced this issue Sep 26, 2021
@fangliu2020 @igcbot
[Autobackout][FuncReg]Revert of change: 69a5cbd
39a826a 
 [vISA]: Fix the WAW/WAR issue of ACC caused by mul/mulh/madw in local scheduling. #2 try.

on some platforms, mul/mulh/madw will be expanded into mul+mach/macl after local scheduling.
Since ACC is used as dst of expanded mul, it is a must to set implicit ACC as dst
of mul/mulh/madw. Otherwise, there will be WAW/WAR issue of ACC in local scheduling.
@haonanya haonanya mentioned this issue Jan 25, 2022
Closed
VPG-SWE-Github pushed a commit that referenced this issue Apr 16, 2022
@dlei6g @igcbot
Map subroutine implicit args to kernel's arg symbol, instead of copy…
74476cc 
…ing (Attempt #2)

We don't need to copy the implicit arg since subroutines have access to the kernel's variables.
Just update the symbol map such that implicit arg intrinsics are mapped to the kernel's formal arguments.
VPG-SWE-Github pushed a commit that referenced this issue Apr 17, 2022
@dlei6g @igcbot
[Autobackout][FuncReg]Revert of change: 74476cc
41cdbfd 
 Map subroutine implicit args to kernel's arg symbol, instead of copying (Attempt #2)

We don't need to copy the implicit arg since subroutines have access to the kernel's variables.
Just update the symbol map such that implicit arg intrinsics are mapped to the kernel's formal arguments.
VPG-SWE-Github pushed a commit that referenced this issue May 19, 2023
@dlei6g @igcbot
Only enable CallWA for SIMD32 when nested stackcalls or indirect cal…
e07cf8a 
…ls are present (Try #2)

Only enable CallWA for SIMD32 when nested stackcalls or indirect calls are present.
Also added FunctionGroupAnalysis Function Group attributes: hasSubroutine() and isIndirectCallGroup(), plus general refactor for FGA and CShader.
VPG-SWE-Github pushed a commit that referenced this issue May 22, 2023
@dlei6g @igcbot
[Autobackout][FuncReg]Revert of change: e07cf8a
7a1db0e 
 Only enable CallWA for SIMD32 when nested stackcalls or indirect calls are present (Try #2)

Only enable CallWA for SIMD32 when nested stackcalls or indirect calls are present.
Also added FunctionGroupAnalysis Function Group attributes: hasSubroutine() and isIndirectCallGroup(), plus general refactor for FGA and CShader.
VPG-SWE-Github pushed a commit that referenced this issue Dec 1, 2023
@fangliu2020 @igcbot
Fix a few register regioning issues for 64b instructions on MTL plat…
43681f8 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.
VPG-SWE-Github pushed a commit that referenced this issue Dec 5, 2023
@fangliu2020 @igcbot
[Autobackout][FuncReg]Revert of change: 43681f8
35cc38f 
 Fix a few register regioning issues for 64b instructions on MTL platform

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.
VPG-SWE-Github pushed a commit that referenced this issue Dec 12, 2023
@fangliu2020 @igcbot
Fix a few register regioning issues for 64b instructions on MTL plat…
620c74c 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.
pszymich pushed a commit that referenced this issue Dec 19, 2023
@fangliu2020 @pszymich
Fix a few register regioning issues for 64b instructions on MTL plat…
d360c48 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.

(cherry picked from commit 43681f8)
pszymich pushed a commit that referenced this issue Dec 20, 2023
@fangliu2020 @pszymich
Fix a few register regioning issues for 64b instructions on MTL plat…
2e9a3f6 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.

(cherry picked from commit 43681f8)
pszymich pushed a commit that referenced this issue Dec 20, 2023
@fangliu2020 @pszymich
Fix a few register regioning issues for 64b instructions on MTL plat…
e11f8e0 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.

(cherry picked from commit 43681f8)
fda0 pushed a commit that referenced this issue Jan 25, 2024
@fangliu2020 @fda0
Fix a few register regioning issues for 64b instructions on MTL plat…
2ae43a7 
…form

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.

(cherry picked from commit 620c74c)
VPG-SWE-Github pushed a commit that referenced this issue May 16, 2025
@bokrzesi @igcbot
Fixing ArgSize calculation for metadata type function argument in Op…
7a45c84 
…enCLPasses -> PrivateMemoryResolution and fix of invalid "sret" LegalizeFunctionSignatures void to struct transformation

In such case

```
...
call void @llvm.experimental.noalias.scope.decl(metadata !805)
...

; Function Attrs: nounwind
declare spir_func %structtype @__devicelib_catanf(%structtype sret(%structtype) align 4 %0) #2

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
declare void @llvm.experimental.noalias.scope.decl(metadata %0) #3

!805 = !{!806}
!806 = distinct !{!806, !807, !"catanf: argument 0"}
!807 = distinct !{!807, !"catanf"}
```

When PrivateMemoryResolution was "recursively calculating the max private mem usage of all callees"
Then during processing function argument that is MetadataTy it was failing due to

```
Assertion failed: Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!",
file ...\dump64\llvm-deps-16.0.6\src\llvm\lib\IR\DataLayout.cpp, line 751
````

So I added check for MetadataTy which skips it.

Additionally `LegalizeFunctionSignatures` was transforming the return type of void function that used sret() as its argument.
The LLVM IR verifier didnt like that since the docs state that:
`A function that accepts an sret argument must return void. A return value may not be sret.`

I've decided to perform skip on sret cases in that pass.
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@ssarangi @AnupamaChandrasekhar