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Xe2_Or_Later flag doesn't handle Xe3 architecture - it treats them as Unknown architectures. #5946

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Description

@BBBela

Several test cases in PyTorch that use torch.xpu._sleep() are gated by @uniitest.skipIf(not Xe2_Or_Later). It makes sense as torch.xpu._sleep() is not supported for Xe1 architecture, for example PVC.

The problem is that effectively the Xe2_Or_Later treats Xe3 as Unknown and for Xe3, the Xe2_Or_Later flag evaluates to False, while the name suggests that it should be True. That is caused by missing entries for newer hardware in _DEVICE_ID_TO_CODENAME dict and _CODENAME_TO_ARCH dict. The mappings are only for PVC and BMG, while newer hardware is treated as Unknown, which currently evaluates always to false in Xe2_Or_Later flag.

This task issue is to consider solution for that problem. I suppose that all the supported hardware ids and codenames should be added and flag evaluation should raise rather than silently categorizing the unknown device type to not Xe2_Or_Later.

The device ids are taken from compiler header file here: FILE

The Xe2_Or_Later is defined in THIS FILE

Activity

  1. self-assigned this
    on Oct 29, 2026
  2. added theissue type on Oct 29, 2026
  3. removed their assignment
    on Oct 29, 2026
  4. changed the title [-]`Xe2_Or_Later` flag doesn't handle Xe3 or Xe4 architecture - it treats them as Unknown architectures.[/-] [+]`Xe2_Or_Later` flag doesn't handle Xe3 architecture - it treats them as Unknown architectures.[/+] on Nov 4, 2026
  5. added
    module: infraOnly for CICD infra used, no action need
    functionalityFunctional defect: error/assert/hang/timeout (non-numeric)
    test: utUnit-test failure surface
    on Nov 9, 2026
  6. daisyden commented on Nov 9, 2026

    @daisyden
    Contributor
    label-issue: #5946

    Root cause: torch/testing/_internal/common_xpu.py:26-56 maps only PVC/BMG ids and codenames; unknown (Xe3) devices fall to
    XPUArch.Unknown (:69), so Xe2_Or_Later (:72-74) is False on Xe3. Test-harness defect in pytorch.

    axis value reason
    type Task Native Type Task preserved.
    test test: ut Affects UT skip gating via Xe2_Or_Later; no e2e/oob signal.
    module module: infra Defect in test-harness helper common_xpu.py:26-74, not an op or runtime surface.
    priority Low Human-set native Priority preserved verbatim.
    symptom functionality Xe2_Or_Later evaluates False on Xe3, wrongly skipping torch.xpu._sleep() tests.

    Applied to this issue. Generated by a local label-issue run.

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    functionalityFunctional defect: error/assert/hang/timeout (non-numeric)module: infraOnly for CICD infra used, no action needtest: utUnit-test failure surface

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