Skip to content

Commit a139def

Browse files
jacobly0jacobly0
committed
Merge with upstream.
1 parent 867c77f commit a139def

15 files changed

+208
-158
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -306,14 +306,6 @@ class CallLowering {
306306
unsigned MaxSizeBits = 0);
307307

308308
virtual bool finalize(CCState &State) { return true; }
309-
310-
MachineIRBuilder &MIRBuilder;
311-
MachineRegisterInfo &MRI;
312-
CCAssignFn *AssignFn;
313-
314-
private:
315-
bool IsIncomingArgumentHandler;
316-
virtual void anchor();
317309
};
318310

319311
/// Base class for ValueHandlers used for arguments coming into the current

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ struct InstrImmPair {
9191

9292
struct TypeImmPair {
9393
LLT Ty;
94-
int64_t Imm;
94+
uint64_t Imm;
9595
};
9696

9797
using OperandBuildSteps =

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,11 @@ class LegalizerHelper {
186186
void extractParts(Register Reg, LLT Ty, int NumParts,
187187
SmallVectorImpl<Register> &VRegs);
188188

189-
/// Version which handles irregular splits.
189+
/// Versions which handle irregular splits.
190+
bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
191+
LLT &LeftoverTy,
192+
SmallVectorImpl<Register> &VRegs,
193+
SmallVectorImpl<Register> &LeftoverVRegs);
190194
bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
191195
SmallVectorImpl<Register> &VRegs, LLT &LeftoverTy,
192196
Register &LeftoverReg);

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1155,7 +1155,8 @@ class LegalizerInfo {
11551155
}
11561156

11571157
virtual LegalizerHelper::LegalizeResult
1158-
legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI) const {
1158+
legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI,
1159+
LostDebugLocObserver &LocObserver) const {
11591160
return legalizeCustom(Helper, MI) ? LegalizerHelper::Legalized
11601161
: LegalizerHelper::UnableToLegalize;
11611162
}

‎llvm/include/llvm/Support/MachineValueType.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1079,7 +1079,7 @@ namespace llvm {
10791079
/// base size.
10801080
TypeSize getStoreSize() const {
10811081
TypeSize BaseSize = getSizeInBits();
1082-
return {(BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable()};
1082+
return {divideCeil(BaseSize.getKnownMinSize(), 8), BaseSize.isScalable()};
10831083
}
10841084

10851085
/// Return the number of bits overwritten by a store of the specified value

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 16 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
135135
else
136136
Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
137137

138-
Info.OrigRet = ArgInfo{ResRegs, CB, ISD::ArgFlagsTy{}};
138+
Info.OrigRet = ArgInfo{ResRegs, CB, 0, ISD::ArgFlagsTy{}};
139139
if (!Info.OrigRet.Ty->isVoidTy())
140140
setArgFlags(Info.OrigRet, AttributeList::ReturnIndex, DL, CB);
141141

@@ -504,7 +504,6 @@ static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,
504504
LLT LCMTy = getLCMType(SrcTy, PartTy);
505505

506506
const unsigned DstSize = DstTy.getSizeInBits();
507-
const unsigned SrcSize = SrcTy.getSizeInBits();
508507
unsigned CoveringSize = LCMTy.getSizeInBits();
509508

510509
Register UnmergeSrc = SrcReg;
@@ -611,10 +610,9 @@ bool CallLowering::determineAssignments(ValueAssigner &Assigner,
611610
Flags.setSplitEnd();
612611
if (!Exact && !CurVT.isVector())
613612
PartVT = TLI->getRegisterTypeForCallingConv(
614-
F.getContext(), CCInfo.getCallingConv(),
615-
EVT::getIntegerVT(F.getContext(),
616-
CurVT.getSizeInBits() -
617-
NewVT.getSizeInBits() * Part));
613+
Ctx, CCInfo.getCallingConv(),
614+
EVT::getIntegerVT(Ctx, CurVT.getSizeInBits() -
615+
NewVT.getSizeInBits() * Part));
618616
}
619617
}
620618

@@ -686,9 +684,11 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
686684
ArgReg = MRI.createGenericVirtualRegister(p0);
687685
else {
688686
MachineFrameInfo &MFI = MF.getFrameInfo();
689-
unsigned Size = ValVT.getStoreSize();
690-
int FI =
691-
MFI.CreateStackObject(Size, DL.getPrefTypeAlign(Args[i].Ty), false);
687+
// TODO: The memory size may be larger than the value we need to
688+
// store. We may need to adjust the offset for big endian targets.
689+
LLT MemTy = Handler.getStackValueStoreType(DL, VA, Args[i].Flags[0]);
690+
int FI = MFI.CreateStackObject(MemTy.getSizeInBytes(),
691+
DL.getPrefTypeAlign(Args[i].Ty), false);
692692
auto StackSlot = MIRBuilder.buildFrameIndex(p0, FI);
693693
LLT sIndex = LLT::scalar(DL.getIndexSizeInBits(0));
694694
ArgReg = {};
@@ -697,9 +697,9 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
697697
MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
698698
CCValAssign IndirectVA = CCValAssign::getMem(i, ValVT, IndirectOffset,
699699
ValVT, CCValAssign::Full);
700-
Handler.assignValueToAddress(Args[i].OrigRegs[0], ArgReg, Size, MPO,
700+
Handler.assignValueToAddress(Args[i].OrigRegs[0], ArgReg, MemTy, MPO,
701701
IndirectVA);
702-
IndirectOffset += Size;
702+
IndirectOffset += MemTy.getSizeInBytes();
703703
}
704704
Args[i].Regs[0] = ArgReg;
705705
}
@@ -819,16 +819,18 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
819819

820820
if (VA.getLocInfo() == CCValAssign::Indirect) {
821821
Register AddrReg;
822-
unsigned Size = ValVT.getStoreSize();
822+
// TODO: The memory size may be larger than the value we need to
823+
// store. We may need to adjust the offset for big endian targets.
824+
LLT MemTy = Handler.getStackValueStoreType(DL, VA, Args[i].Flags[0]);
823825
LLT sIndex = LLT::scalar(DL.getIndexSizeInBits(0));
824826
MIRBuilder.materializePtrAdd(AddrReg, Args[i].Regs[0], sIndex,
825827
IndirectOffset);
826828
MachinePointerInfo MPO(Args[i].OrigValue, IndirectOffset);
827829
CCValAssign IndirectVA =
828830
CCValAssign::getMem(i, ValVT, IndirectOffset, ValVT, CCValAssign::Full);
829-
Handler.assignValueToAddress(Args[i].OrigRegs[0], AddrReg, Size, MPO,
831+
Handler.assignValueToAddress(Args[i].OrigRegs[0], AddrReg, MemTy, MPO,
830832
IndirectVA);
831-
IndirectOffset += Size;
833+
IndirectOffset += MemTy.getSizeInBytes();
832834
}
833835
}
834836

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4546,7 +4546,7 @@ bool CombinerHelper::applyCombineOrToAdd(MachineInstr &MI) {
45464546
bool CombinerHelper::matchCombineFunnelShift(MachineInstr &MI,
45474547
FunnelShift &MatchInfo) {
45484548
Register DstReg = MI.getOperand(0).getReg();
4549-
int64_t ShiftRightAmt;
4549+
uint64_t ShiftRightAmt;
45504550
return mi_match(DstReg, MRI,
45514551
m_GAdd(m_GShl(m_Reg(MatchInfo.ShiftLeftReg),
45524552
m_ICst(MatchInfo.ShiftLeftAmt)),

‎llvm/lib/CodeGen/GlobalISel/Legalizer.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,6 @@ static bool isArtifact(const MachineInstr &MI) {
110110
case TargetOpcode::G_CONCAT_VECTORS:
111111
case TargetOpcode::G_BUILD_VECTOR:
112112
case TargetOpcode::G_EXTRACT:
113-
case TargetOpcode::G_INSERT:
114113
return true;
115114
case TargetOpcode::G_INSERT:
116115
return AllowGInsertAsArtifact;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 81 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ LegalizerHelper::legalizeInstrStep(MachineInstr &MI,
143143
return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
144144
case Custom:
145145
LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
146-
return LI.legalizeCustomMaybeLegal(*this, MI);
146+
return LI.legalizeCustomMaybeLegal(*this, MI, LocObserver);
147147
default:
148148
LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
149149
return UnableToLegalize;
@@ -162,6 +162,52 @@ void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
162162
MIRBuilder.buildUnmerge(VRegs, Reg);
163163
}
164164

165+
bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
166+
LLT MainTy, LLT &LeftoverTy,
167+
SmallVectorImpl<Register> &VRegs,
168+
SmallVectorImpl<Register> &LeftoverRegs) {
169+
assert(!LeftoverTy.isValid() && "this is an out argument");
170+
171+
unsigned RegSize = RegTy.getSizeInBits();
172+
unsigned MainSize = MainTy.getSizeInBits();
173+
unsigned NumParts = RegSize / MainSize;
174+
unsigned LeftoverSize = RegSize - NumParts * MainSize;
175+
176+
// Use an unmerge when possible.
177+
if (LeftoverSize == 0) {
178+
for (unsigned I = 0; I < NumParts; ++I)
179+
VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
180+
MIRBuilder.buildUnmerge(VRegs, Reg);
181+
return true;
182+
}
183+
184+
if (MainTy.isVector()) {
185+
unsigned EltSize = MainTy.getScalarSizeInBits();
186+
if (LeftoverSize % EltSize != 0)
187+
return false;
188+
LeftoverTy = LLT::scalarOrVector(
189+
ElementCount::getFixed(LeftoverSize / EltSize), EltSize);
190+
} else {
191+
LeftoverTy = LLT::scalar(LeftoverSize);
192+
}
193+
194+
// For irregular sizes, extract the individual parts.
195+
for (unsigned I = 0; I != NumParts; ++I) {
196+
Register NewReg = MRI.createGenericVirtualRegister(MainTy);
197+
VRegs.push_back(NewReg);
198+
MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
199+
}
200+
201+
for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
202+
Offset += LeftoverSize) {
203+
Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
204+
LeftoverRegs.push_back(NewReg);
205+
MIRBuilder.buildExtract(NewReg, Reg, Offset);
206+
}
207+
208+
return true;
209+
}
210+
165211
bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, LLT MainTy,
166212
SmallVectorImpl<Register> &VRegs,
167213
LLT &LeftoverTy, Register &LeftoverReg) {
@@ -795,8 +841,8 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
795841
unsigned OpSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
796842
Type *OpTy = IntegerType::get(Ctx, OpSize);
797843
RTLIB::Libcall Libcall = getRTLibDesc(MI.getOpcode(), OpSize);
798-
createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ResTy},
799-
{{MI.getOperand(1).getReg(), OpTy}});
844+
createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ResTy, 0},
845+
{{MI.getOperand(1).getReg(), OpTy, 0}});
800846
break;
801847
}
802848
case TargetOpcode::G_SHL:
@@ -807,8 +853,9 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
807853
Register AmountReg = MI.getOperand(2).getReg();
808854
Type *AmountTy =
809855
IntegerType::get(Ctx, MRI.getType(AmountReg).getSizeInBits());
810-
createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpTy},
811-
{{MI.getOperand(1).getReg(), OpTy}, {AmountReg, AmountTy}});
856+
createLibcall(
857+
MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpTy, 0},
858+
{{MI.getOperand(1).getReg(), OpTy, 0}, {AmountReg, AmountTy, 0}});
812859
break;
813860
}
814861
case TargetOpcode::G_INTRINSIC_TRUNC:
@@ -4238,17 +4285,22 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
42384285
return UnableToLegalize;
42394286
}
42404287

4241-
unsigned NumParts = 0;
4288+
int NumParts = -1;
4289+
int NumLeftover = -1;
42424290
LLT LeftoverTy;
4243-
SmallVector<Register, 8> NarrowRegs;
4244-
Register NarrowLeftoverReg;
4291+
SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
42454292
if (IsLoad) {
42464293
NumParts = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
4247-
NarrowRegs.resize(NumParts);
4248-
} else if (extractParts(ValReg, ValTy, NarrowTy, NarrowRegs, LeftoverTy,
4249-
NarrowLeftoverReg))
4250-
NumParts = NarrowRegs.size();
4251-
if (!NumParts)
4294+
NumLeftover = LeftoverTy.isValid();
4295+
} else {
4296+
if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
4297+
NarrowLeftoverRegs)) {
4298+
NumParts = NarrowRegs.size();
4299+
NumLeftover = NarrowLeftoverRegs.size();
4300+
}
4301+
}
4302+
4303+
if (NumParts == -1)
42524304
return UnableToLegalize;
42534305

42544306
LLT PtrTy = MRI.getType(AddrReg);
@@ -4272,16 +4324,16 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
42724324

42734325
MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
42744326

4275-
MachineMemOperand *NewMMO =
4276-
MF.getMachineMemOperand(&MMO, ByteOffset, PartTy);
4327+
MachineMemOperand *NewMMO =
4328+
MF.getMachineMemOperand(&MMO, ByteOffset, PartTy);
42774329

4278-
if (IsLoad) {
4279-
Register Dst = MRI.createGenericVirtualRegister(PartTy);
4280-
ValRegs[Idx] = Dst;
4281-
MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
4282-
} else {
4283-
MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
4284-
}
4330+
if (IsLoad) {
4331+
Register Dst = MRI.createGenericVirtualRegister(PartTy);
4332+
ValRegs.push_back(Dst);
4333+
MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
4334+
} else {
4335+
MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
4336+
}
42854337
}
42864338

42874339
return Offset;
@@ -4291,11 +4343,12 @@ LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx,
42914343

42924344
// Handle the rest of the register if this isn't an even type breakdown.
42934345
if (LeftoverTy.isValid())
4294-
splitTypePieces(LeftoverTy, NarrowLeftoverReg, HandledOffset);
4346+
splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
42954347

4296-
if (IsLoad)
4348+
if (IsLoad) {
42974349
insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, LeftoverTy,
4298-
NarrowLeftoverReg);
4350+
NarrowLeftoverRegs[0]);
4351+
}
42994352

43004353
LdStMI.eraseFromParent();
43014354
return Legalized;
@@ -5508,15 +5561,13 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
55085561
return UnableToLegalize;
55095562

55105563
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
5511-
unsigned NarrowSize = NarrowTy.getSizeInBits();
5564+
uint64_t NarrowSize = NarrowTy.getSizeInBits();
55125565

55135566
// FIXME: add support for when DstSize isn't an exact multiple of
55145567
// NarrowSize.
55155568
if (DstSize % NarrowSize != 0)
55165569
return UnableToLegalize;
55175570

5518-
int NumParts = DstSize / NarrowSize;
5519-
55205571
SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs;
55215572
SmallVector<uint64_t, 2> Indexes;
55225573
LLT RegTy = MRI.getType(MI.getOperand(0).getReg());
@@ -5527,7 +5578,6 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
55275578
for (Register Reg : LeftoverRegs)
55285579
SrcRegs.push_back(Reg);
55295580

5530-
uint64_t NarrowSize = NarrowTy.getSizeInBits();
55315581
Register OpReg = MI.getOperand(2).getReg();
55325582
uint64_t OpStart = MI.getOperand(3).getImm();
55335583
uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
@@ -5556,8 +5606,8 @@ LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
55565606

55575607
// OpSegStart is where this destination segment would start in OpReg if it
55585608
// extended infinitely in both directions.
5559-
unsigned ExtractOffset, InsertOffset;
5560-
unsigned SegSize;
5609+
int64_t ExtractOffset, InsertOffset;
5610+
uint64_t SegSize;
55615611
if (OpStart < DstStart) {
55625612
InsertOffset = 0;
55635613
ExtractOffset = DstStart - OpStart;

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1230,7 +1230,7 @@ bool AMDGPUCallLowering::lowerTailCall(
12301230
if (MIB->getOperand(0).isReg()) {
12311231
MIB->getOperand(0).setReg(constrainOperandRegClass(
12321232
MF, *TRI, MRI, *ST.getInstrInfo(), *ST.getRegBankInfo(), *MIB,
1233-
MIB->getDesc(), MIB->getOperand(0), 0));
1233+
MIB->getOperand(0), 0));
12341234
}
12351235

12361236
MF.getFrameInfo().setHasTailCall();

0 commit comments

Comments
 (0)