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Checkpointing is finally here!!! 🎉 (it took a bit of work and debug)
Integrates rollback-on-branch-misprediction flow and use of instruction tags into the core.
Async interrupts and other exceptions are still handled by flushing the old way.
TODO:
fix other unit tests, verify linux boot, verify benchmarks
yeah, it is, but I expected it to be bigger (hope that's not a wishful thinking). Did you have any expectations of it?
Also hoped for a bigger difference, but it looks like there are other factors at play. A few of the most obvious for me are:
Mispredictions still have a cost (filling the pipeline, keeping the functional units busy with not needed operations).
The core cannot execute dependent instructions cycle after cycle as there is no forwarding from instruction results to RS (and full forwarding would probably be costly to implement). Superscalarity would help discover independent instructions faster.
According to metrics, quite a lot of instructions seem to linger in RS for some time. There could be multiple reasons for that: maybe the results are not coming in fast enough, or maybe the other end of the pipeline is the limiting factor. I would consider adding more metrics to RS to help understand the behavior.
Lack of superscalarity means that if multiple instructions in different RS have their operand ready in the same cycle, they still need to complete in sequence.
The LSU blocks reordering of instructions.
It's hard to decide the importance of these factors on the final performance. There is probably no single biggest reason, I'm starting to believe that OoO performance is complex and comes from a combination of many factors.
Given that benchmarks and other full core tests work fine, most probably the issue is related to M-mode and interrupt handling. Indeed RISCV-DV claims to cover this.
finally made a merge with superscalarity, new frontend and other changes.
stopped working correctly on core and checkpointing tests.
needs further investigation
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benchmarkBenchmarks should be run for this changeenhancementNew feature or requestmicroarchInvolves the processor's microarchitecturenlnetThe work is part of the NLnet grantperformanceImproves performance
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Checkpointing is finally here!!! 🎉 (it took a bit of work and debug)
Integrates rollback-on-branch-misprediction flow and use of instruction tags into the core.
Async interrupts and other exceptions are still handled by flushing the old way.
TODO:
fix other unit tests, verify linux boot, verify benchmarks