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[Mips] In LowerShift*Parts, xor with bits-1 instead of -1. (#71149)
If we start with an i128 shift, the initial shift amount would usually have zeros in bit 8 and above. xoring the shift amount with -1 will set those upper bits to 1. If DAGCombiner is able to prove those bits are now 1, then the shift that uses the xor will be replaced with undef. Which we don't want. Reduce the xor constant to VT.bits-1 where VT is half the size of the larger shift type. This avoids toggling the upper bits. The hardware shift instruction only uses the lower bits of the shift amount. I assume the code used NOT because the hardware doesn't use the upper bits, but that isn't compatible with the LLVM poison semantics. Fixes #71142.
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‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2593,12 +2593,13 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
25932593
SDValue Shamt = Op.getOperand(2);
25942594
// if shamt < (VT.bits):
25952595
// lo = (shl lo, shamt)
2596-
// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2596+
// hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1))))
25972597
// else:
25982598
// lo = 0
25992599
// hi = (shl lo, shamt[4:0])
2600-
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2601-
DAG.getConstant(-1, DL, MVT::i32));
2600+
SDValue Not =
2601+
DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2602+
DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
26022603
SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
26032604
DAG.getConstant(1, DL, VT));
26042605
SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
@@ -2623,7 +2624,7 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
26232624
MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
26242625

26252626
// if shamt < (VT.bits):
2626-
// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2627+
// lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt))
26272628
// if isSRA:
26282629
// hi = (sra hi, shamt)
26292630
// else:
@@ -2635,8 +2636,9 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
26352636
// else:
26362637
// lo = (srl hi, shamt[4:0])
26372638
// hi = 0
2638-
SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2639-
DAG.getConstant(-1, DL, MVT::i32));
2639+
SDValue Not =
2640+
DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2641+
DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32));
26402642
SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
26412643
DAG.getConstant(1, DL, VT));
26422644
SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);

‎llvm/test/CodeGen/Mips/llvm-ir/ashr.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
280280
; MIPS-NEXT: srav $3, $4, $7
281281
; MIPS-NEXT: # %bb.1: # %entry
282282
; MIPS-NEXT: srlv $1, $5, $7
283-
; MIPS-NEXT: not $2, $7
283+
; MIPS-NEXT: xori $2, $7, 31
284284
; MIPS-NEXT: sll $4, $4, 1
285285
; MIPS-NEXT: sllv $2, $4, $2
286286
; MIPS-NEXT: or $1, $2, $1
@@ -294,7 +294,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
294294
; MIPS32-LABEL: ashr_i64:
295295
; MIPS32: # %bb.0: # %entry
296296
; MIPS32-NEXT: srlv $1, $5, $7
297-
; MIPS32-NEXT: not $2, $7
297+
; MIPS32-NEXT: xori $2, $7, 31
298298
; MIPS32-NEXT: sll $3, $4, 1
299299
; MIPS32-NEXT: sllv $2, $3, $2
300300
; MIPS32-NEXT: or $3, $2, $1
@@ -308,7 +308,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
308308
; 32R2-LABEL: ashr_i64:
309309
; 32R2: # %bb.0: # %entry
310310
; 32R2-NEXT: srlv $1, $5, $7
311-
; 32R2-NEXT: not $2, $7
311+
; 32R2-NEXT: xori $2, $7, 31
312312
; 32R2-NEXT: sll $3, $4, 1
313313
; 32R2-NEXT: sllv $2, $3, $2
314314
; 32R2-NEXT: or $3, $2, $1
@@ -328,7 +328,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
328328
; 32R6-NEXT: selnez $6, $6, $3
329329
; 32R6-NEXT: or $2, $6, $2
330330
; 32R6-NEXT: srlv $5, $5, $7
331-
; 32R6-NEXT: not $6, $7
331+
; 32R6-NEXT: xori $6, $7, 31
332332
; 32R6-NEXT: sll $4, $4, 1
333333
; 32R6-NEXT: sllv $4, $4, $6
334334
; 32R6-NEXT: or $4, $4, $5
@@ -360,9 +360,9 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
360360
; MMR3-LABEL: ashr_i64:
361361
; MMR3: # %bb.0: # %entry
362362
; MMR3-NEXT: srlv $2, $5, $7
363-
; MMR3-NEXT: not16 $3, $7
364-
; MMR3-NEXT: sll16 $5, $4, 1
365-
; MMR3-NEXT: sllv $3, $5, $3
363+
; MMR3-NEXT: xori $1, $7, 31
364+
; MMR3-NEXT: sll16 $3, $4, 1
365+
; MMR3-NEXT: sllv $3, $3, $1
366366
; MMR3-NEXT: or16 $3, $2
367367
; MMR3-NEXT: srav $2, $4, $7
368368
; MMR3-NEXT: andi16 $5, $7, 32
@@ -380,7 +380,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
380380
; MMR6-NEXT: selnez $6, $6, $3
381381
; MMR6-NEXT: or $2, $6, $2
382382
; MMR6-NEXT: srlv $5, $5, $7
383-
; MMR6-NEXT: not16 $6, $7
383+
; MMR6-NEXT: xori $6, $7, 31
384384
; MMR6-NEXT: sll16 $4, $4, 1
385385
; MMR6-NEXT: sllv $4, $4, $6
386386
; MMR6-NEXT: or $4, $4, $5
@@ -609,7 +609,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
609609
; MIPS3-NEXT: # %bb.1: # %entry
610610
; MIPS3-NEXT: dsrlv $1, $5, $7
611611
; MIPS3-NEXT: dsll $4, $4, 1
612-
; MIPS3-NEXT: not $2, $2
612+
; MIPS3-NEXT: xori $2, $2, 63
613613
; MIPS3-NEXT: dsllv $2, $4, $2
614614
; MIPS3-NEXT: or $1, $2, $1
615615
; MIPS3-NEXT: move $2, $3
@@ -624,7 +624,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
624624
; MIPS64-NEXT: dsrlv $1, $5, $7
625625
; MIPS64-NEXT: dsll $2, $4, 1
626626
; MIPS64-NEXT: sll $5, $7, 0
627-
; MIPS64-NEXT: not $3, $5
627+
; MIPS64-NEXT: xori $3, $5, 63
628628
; MIPS64-NEXT: dsllv $2, $2, $3
629629
; MIPS64-NEXT: or $3, $2, $1
630630
; MIPS64-NEXT: dsrav $2, $4, $7
@@ -639,7 +639,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
639639
; MIPS64R2-NEXT: dsrlv $1, $5, $7
640640
; MIPS64R2-NEXT: dsll $2, $4, 1
641641
; MIPS64R2-NEXT: sll $5, $7, 0
642-
; MIPS64R2-NEXT: not $3, $5
642+
; MIPS64R2-NEXT: xori $3, $5, 63
643643
; MIPS64R2-NEXT: dsllv $2, $2, $3
644644
; MIPS64R2-NEXT: or $3, $2, $1
645645
; MIPS64R2-NEXT: dsrav $2, $4, $7
@@ -661,7 +661,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
661661
; MIPS64R6-NEXT: or $2, $8, $2
662662
; MIPS64R6-NEXT: dsrlv $5, $5, $7
663663
; MIPS64R6-NEXT: dsll $4, $4, 1
664-
; MIPS64R6-NEXT: not $3, $3
664+
; MIPS64R6-NEXT: xori $3, $3, 63
665665
; MIPS64R6-NEXT: dsllv $3, $4, $3
666666
; MIPS64R6-NEXT: or $3, $3, $5
667667
; MIPS64R6-NEXT: seleqz $3, $3, $6

‎llvm/test/CodeGen/Mips/llvm-ir/lshr.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
283283
; MIPS2-NEXT: addiu $2, $zero, 0
284284
; MIPS2-NEXT: # %bb.1: # %entry
285285
; MIPS2-NEXT: srlv $1, $5, $7
286-
; MIPS2-NEXT: not $2, $7
286+
; MIPS2-NEXT: xori $2, $7, 31
287287
; MIPS2-NEXT: sll $3, $4, 1
288288
; MIPS2-NEXT: sllv $2, $3, $2
289289
; MIPS2-NEXT: or $3, $2, $1
@@ -296,7 +296,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
296296
; MIPS32-LABEL: lshr_i64:
297297
; MIPS32: # %bb.0: # %entry
298298
; MIPS32-NEXT: srlv $1, $5, $7
299-
; MIPS32-NEXT: not $2, $7
299+
; MIPS32-NEXT: xori $2, $7, 31
300300
; MIPS32-NEXT: sll $3, $4, 1
301301
; MIPS32-NEXT: sllv $2, $3, $2
302302
; MIPS32-NEXT: or $3, $2, $1
@@ -309,7 +309,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
309309
; MIPS32R2-LABEL: lshr_i64:
310310
; MIPS32R2: # %bb.0: # %entry
311311
; MIPS32R2-NEXT: srlv $1, $5, $7
312-
; MIPS32R2-NEXT: not $2, $7
312+
; MIPS32R2-NEXT: xori $2, $7, 31
313313
; MIPS32R2-NEXT: sll $3, $4, 1
314314
; MIPS32R2-NEXT: sllv $2, $3, $2
315315
; MIPS32R2-NEXT: or $3, $2, $1
@@ -322,7 +322,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
322322
; MIPS32R6-LABEL: lshr_i64:
323323
; MIPS32R6: # %bb.0: # %entry
324324
; MIPS32R6-NEXT: srlv $1, $5, $7
325-
; MIPS32R6-NEXT: not $2, $7
325+
; MIPS32R6-NEXT: xori $2, $7, 31
326326
; MIPS32R6-NEXT: sll $3, $4, 1
327327
; MIPS32R6-NEXT: sllv $2, $3, $2
328328
; MIPS32R6-NEXT: or $1, $2, $1
@@ -362,9 +362,9 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
362362
; MMR3-LABEL: lshr_i64:
363363
; MMR3: # %bb.0: # %entry
364364
; MMR3-NEXT: srlv $2, $5, $7
365-
; MMR3-NEXT: not16 $3, $7
366-
; MMR3-NEXT: sll16 $5, $4, 1
367-
; MMR3-NEXT: sllv $3, $5, $3
365+
; MMR3-NEXT: xori $1, $7, 31
366+
; MMR3-NEXT: sll16 $3, $4, 1
367+
; MMR3-NEXT: sllv $3, $3, $1
368368
; MMR3-NEXT: or16 $3, $2
369369
; MMR3-NEXT: srlv $2, $4, $7
370370
; MMR3-NEXT: andi16 $4, $7, 32
@@ -376,7 +376,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
376376
; MMR6-LABEL: lshr_i64:
377377
; MMR6: # %bb.0: # %entry
378378
; MMR6-NEXT: srlv $1, $5, $7
379-
; MMR6-NEXT: not16 $2, $7
379+
; MMR6-NEXT: xori $2, $7, 31
380380
; MMR6-NEXT: sll16 $3, $4, 1
381381
; MMR6-NEXT: sllv $2, $3, $2
382382
; MMR6-NEXT: or $1, $2, $1
@@ -606,7 +606,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
606606
; MIPS3-NEXT: # %bb.1: # %entry
607607
; MIPS3-NEXT: dsrlv $1, $5, $7
608608
; MIPS3-NEXT: dsll $2, $4, 1
609-
; MIPS3-NEXT: not $3, $3
609+
; MIPS3-NEXT: xori $3, $3, 63
610610
; MIPS3-NEXT: dsllv $2, $2, $3
611611
; MIPS3-NEXT: or $3, $2, $1
612612
; MIPS3-NEXT: jr $ra
@@ -620,7 +620,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
620620
; MIPS4-NEXT: dsrlv $1, $5, $7
621621
; MIPS4-NEXT: dsll $2, $4, 1
622622
; MIPS4-NEXT: sll $5, $7, 0
623-
; MIPS4-NEXT: not $3, $5
623+
; MIPS4-NEXT: xori $3, $5, 63
624624
; MIPS4-NEXT: dsllv $2, $2, $3
625625
; MIPS4-NEXT: or $3, $2, $1
626626
; MIPS4-NEXT: dsrlv $2, $4, $7
@@ -634,7 +634,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
634634
; MIPS64-NEXT: dsrlv $1, $5, $7
635635
; MIPS64-NEXT: dsll $2, $4, 1
636636
; MIPS64-NEXT: sll $5, $7, 0
637-
; MIPS64-NEXT: not $3, $5
637+
; MIPS64-NEXT: xori $3, $5, 63
638638
; MIPS64-NEXT: dsllv $2, $2, $3
639639
; MIPS64-NEXT: or $3, $2, $1
640640
; MIPS64-NEXT: dsrlv $2, $4, $7
@@ -648,7 +648,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
648648
; MIPS64R2-NEXT: dsrlv $1, $5, $7
649649
; MIPS64R2-NEXT: dsll $2, $4, 1
650650
; MIPS64R2-NEXT: sll $5, $7, 0
651-
; MIPS64R2-NEXT: not $3, $5
651+
; MIPS64R2-NEXT: xori $3, $5, 63
652652
; MIPS64R2-NEXT: dsllv $2, $2, $3
653653
; MIPS64R2-NEXT: or $3, $2, $1
654654
; MIPS64R2-NEXT: dsrlv $2, $4, $7
@@ -662,7 +662,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
662662
; MIPS64R6-NEXT: dsrlv $1, $5, $7
663663
; MIPS64R6-NEXT: dsll $2, $4, 1
664664
; MIPS64R6-NEXT: sll $3, $7, 0
665-
; MIPS64R6-NEXT: not $5, $3
665+
; MIPS64R6-NEXT: xori $5, $3, 63
666666
; MIPS64R6-NEXT: dsllv $2, $2, $5
667667
; MIPS64R6-NEXT: or $1, $2, $1
668668
; MIPS64R6-NEXT: andi $2, $3, 64

‎llvm/test/CodeGen/Mips/llvm-ir/shl.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
343343
; MIPS2-NEXT: nop
344344
; MIPS2-NEXT: $BB4_3: # %entry
345345
; MIPS2-NEXT: sllv $1, $4, $7
346-
; MIPS2-NEXT: not $2, $7
346+
; MIPS2-NEXT: xori $2, $7, 31
347347
; MIPS2-NEXT: srl $3, $5, 1
348348
; MIPS2-NEXT: srlv $2, $3, $2
349349
; MIPS2-NEXT: or $2, $1, $2
@@ -356,7 +356,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
356356
; MIPS32-LABEL: shl_i64:
357357
; MIPS32: # %bb.0: # %entry
358358
; MIPS32-NEXT: sllv $1, $4, $7
359-
; MIPS32-NEXT: not $2, $7
359+
; MIPS32-NEXT: xori $2, $7, 31
360360
; MIPS32-NEXT: srl $3, $5, 1
361361
; MIPS32-NEXT: srlv $2, $3, $2
362362
; MIPS32-NEXT: or $2, $1, $2
@@ -369,7 +369,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
369369
; MIPS32R2-LABEL: shl_i64:
370370
; MIPS32R2: # %bb.0: # %entry
371371
; MIPS32R2-NEXT: sllv $1, $4, $7
372-
; MIPS32R2-NEXT: not $2, $7
372+
; MIPS32R2-NEXT: xori $2, $7, 31
373373
; MIPS32R2-NEXT: srl $3, $5, 1
374374
; MIPS32R2-NEXT: srlv $2, $3, $2
375375
; MIPS32R2-NEXT: or $2, $1, $2
@@ -382,7 +382,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
382382
; MIPS32R6-LABEL: shl_i64:
383383
; MIPS32R6: # %bb.0: # %entry
384384
; MIPS32R6-NEXT: sllv $1, $4, $7
385-
; MIPS32R6-NEXT: not $2, $7
385+
; MIPS32R6-NEXT: xori $2, $7, 31
386386
; MIPS32R6-NEXT: srl $3, $5, 1
387387
; MIPS32R6-NEXT: srlv $2, $3, $2
388388
; MIPS32R6-NEXT: or $1, $1, $2
@@ -422,9 +422,9 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
422422
; MMR3-LABEL: shl_i64:
423423
; MMR3: # %bb.0: # %entry
424424
; MMR3-NEXT: sllv $3, $4, $7
425-
; MMR3-NEXT: not16 $2, $7
426-
; MMR3-NEXT: srl16 $4, $5, 1
427-
; MMR3-NEXT: srlv $2, $4, $2
425+
; MMR3-NEXT: xori $1, $7, 31
426+
; MMR3-NEXT: srl16 $2, $5, 1
427+
; MMR3-NEXT: srlv $2, $2, $1
428428
; MMR3-NEXT: or16 $2, $3
429429
; MMR3-NEXT: sllv $3, $5, $7
430430
; MMR3-NEXT: andi16 $4, $7, 32
@@ -436,7 +436,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
436436
; MMR6-LABEL: shl_i64:
437437
; MMR6: # %bb.0: # %entry
438438
; MMR6-NEXT: sllv $1, $4, $7
439-
; MMR6-NEXT: not16 $2, $7
439+
; MMR6-NEXT: xori $2, $7, 31
440440
; MMR6-NEXT: srl16 $3, $5, 1
441441
; MMR6-NEXT: srlv $2, $3, $2
442442
; MMR6-NEXT: or $1, $1, $2
@@ -668,7 +668,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
668668
; MIPS3-NEXT: .LBB5_3: # %entry
669669
; MIPS3-NEXT: dsllv $1, $4, $7
670670
; MIPS3-NEXT: dsrl $2, $5, 1
671-
; MIPS3-NEXT: not $3, $3
671+
; MIPS3-NEXT: xori $3, $3, 63
672672
; MIPS3-NEXT: dsrlv $2, $2, $3
673673
; MIPS3-NEXT: or $2, $1, $2
674674
; MIPS3-NEXT: bnez $8, .LBB5_2
@@ -682,7 +682,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
682682
; MIPS4-NEXT: dsllv $1, $4, $7
683683
; MIPS4-NEXT: dsrl $2, $5, 1
684684
; MIPS4-NEXT: sll $4, $7, 0
685-
; MIPS4-NEXT: not $3, $4
685+
; MIPS4-NEXT: xori $3, $4, 63
686686
; MIPS4-NEXT: dsrlv $2, $2, $3
687687
; MIPS4-NEXT: or $2, $1, $2
688688
; MIPS4-NEXT: dsllv $3, $5, $7
@@ -696,7 +696,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
696696
; MIPS64-NEXT: dsllv $1, $4, $7
697697
; MIPS64-NEXT: dsrl $2, $5, 1
698698
; MIPS64-NEXT: sll $4, $7, 0
699-
; MIPS64-NEXT: not $3, $4
699+
; MIPS64-NEXT: xori $3, $4, 63
700700
; MIPS64-NEXT: dsrlv $2, $2, $3
701701
; MIPS64-NEXT: or $2, $1, $2
702702
; MIPS64-NEXT: dsllv $3, $5, $7
@@ -710,7 +710,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
710710
; MIPS64R2-NEXT: dsllv $1, $4, $7
711711
; MIPS64R2-NEXT: dsrl $2, $5, 1
712712
; MIPS64R2-NEXT: sll $4, $7, 0
713-
; MIPS64R2-NEXT: not $3, $4
713+
; MIPS64R2-NEXT: xori $3, $4, 63
714714
; MIPS64R2-NEXT: dsrlv $2, $2, $3
715715
; MIPS64R2-NEXT: or $2, $1, $2
716716
; MIPS64R2-NEXT: dsllv $3, $5, $7
@@ -724,7 +724,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
724724
; MIPS64R6-NEXT: dsllv $1, $4, $7
725725
; MIPS64R6-NEXT: dsrl $2, $5, 1
726726
; MIPS64R6-NEXT: sll $3, $7, 0
727-
; MIPS64R6-NEXT: not $4, $3
727+
; MIPS64R6-NEXT: xori $4, $3, 63
728728
; MIPS64R6-NEXT: dsrlv $2, $2, $4
729729
; MIPS64R6-NEXT: or $1, $1, $2
730730
; MIPS64R6-NEXT: andi $2, $3, 64

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