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define range(i320, -131070) <4 x i32> @manual_mule(<8 x i16> %a, <8 x i16> %b) unnamed_addr {
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i320, i322, i324, i326>
%1 = zext <4 x i16> %0to <4 x i32>
%2 = shufflevector <8 x i16> %b, <8 x i16> poison, <4 x i32> <i320, i322, i324, i326>
%3 = zext <4 x i16> %2to <4 x i32>
%4 = mulnuw <4 x i32> %3, %1ret <4 x i32> %4
}
does not optimize to the expected output of vec_mule, a single vmleh instruction. The same is true for the other multiplication flavors (low, high, odd).
The text was updated successfully, but these errors were encountered:
by extension I think the widening multiplication should also merge into subsequent additions, so that vec_mule(a, b) + c is equal to vec_meadd(a, b, c). That doesn't seem to be happening today either.
…ation
Detect (non-intrinsic) IR patterns corresponding to the semantics
of the various widening and high-word multiplication instructions.
Specifically, this is done by:
- Recognizing even/odd widening multiplication patterns in DAGCombine
- Recognizing widening multiply-and-add on top during ISel
- Implementing the standard MULHS/MUHLU IR opcodes
- Detecting high-word multiply-and-add (which common code does not)
Depending on architecture level, this can support all integer
vector types as well as the scalar i128 type.
Fixes: llvm/llvm-project#129705
this LLVM
https://godbolt.org/z/cx8adPc9f
does not optimize to the expected output of
vec_mule
, a singlevmleh
instruction. The same is true for the other multiplication flavors (low, high, odd).The text was updated successfully, but these errors were encountered: