Unable to assign paired register for inline asm with 64-bit data on ARM

[llvmbot]

Bugzilla Link	13622
Resolution	FIXED
Resolved on	Feb 21, 2014 05:20
Version	trunk
OS	All
Blocks	llvm/llvm-bugzilla-archive#18926
Attachments	test case
Reporter	LLVM Bugzilla Contributor
CC	@asl,@efriedma-quic,@rengolin,@tinti

Extended Description

on ARM, for the following C code:

typedef unsigned long long u64;

void i64_write(u64 *p, u64 val)
{
u64 tmp;

__asm__ __volatile__(

"1: ldrexd %0, %H0, [%2]\n"
" strexd %0, %3, %H3, [%2]\n"
" teq %0, #​0\n"
" bne 1b"
: "=&r" (tmp), "=Qo" (*p)
: "r" (p), "r" (val)
: "cc");
}

It gives error like:
/tmp/write-D5hDGg.s: Assembler messages:
/tmp/write-D5hDGg.s:14: Error: even register required -- `ldrexd r1,r1,[r0]'

Here is the asm it generates:
i64_write:
@app
1: ldrexd r1, r1, [r0]
strexd r1, r2, r3, [r0]
teq r1, #​0
bne 1b
@NO_APP
bx lr

This is because it assigns r1 to %0 (tmp). However, for 64-bit data, it should allocate even/odd reg pair.

One workaround is to hard code register pairs for i64 types. This is the similar way that ARM deals with ldrexd/strexd intrinsics. (In ARMISelDAGToDAG.cpp, ldrexd/strexd get hard coded registers: R0,R1, before register allocation pass)

[llvmbot]

Fixed by patches:
r175008, r173833, r168229, r168207, r166816

[llvmbot]

I'm still seeing this issue (on almost identical code) in llvm rev. 176491, clang rev. 176480.

Code in question is:

static inline void tf_write_reg64(void *comm_buffer, u64 value)
{
u64 tmp;

    __asm__ __volatile__("@ tf_write_reg64\n"
            "1:     ldrexd %0, [%2]\n"
            "       strexd %0, %1, [%2]\n"
            "       teq    %0, #​0\n"
            "       bne    1b"
            : "=&r" (tmp)
            : "r" (value), "r" (comm_buffer)
            : "cc"
    );

}

Generated code is:

.Ltmp7:
.loc 73 83 0
@​APP
@ tf_write_reg64
1: ldrexd r5, [r3]
strexd r5, r0, [r3]
teq r5, #​0
bne 1b
@​NO_APP

(Note the ldrexd r5, [r3] -- r5 is an odd register)

[llvmbot]

(changing platform to Other/All as the target is arm w/ any OS)

[llvmbot]

when you use
ldrexd %0, [%2]
strexd %0, %1, [%2]

it assumes %0, %1, %2 are independent regs.

Instead, you should use %n %Hn.
For you code, GCC also gives invalid asm:

@ tf_write_reg64

1: ldrexd r4, [r1]
strexd r4, r2, [r1]
teq r4, #​0
bne 1b

[berolinux]

Fix
This patch fixes it -- admittedly a little ugly, but the beginnings of just that workaround were already there before...

[tinti]

Bernhard's patch has fixed my issue in both runtime and compile time.

Also I know a commit of LLVM in which these problems do not happen: baabdec

Here the list of commits applied on the same file as Bernhard's patch after this commit.
ac6d9be Track IR ordering of SelectionDAG nodes 2/4.
c6af243 Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
2a8bea7 ArrayRefize getMachineNode(). No functionality change.
f793de7 Don't glue users to extract_subreg when selecting the llvm.arm.ldrexd intrinsic - it can cause impossible-to-schedule subgraphs to be introduced.
3853f74 ArrayRefize some code. No functionality change.
7248451 Re-apply r175088 for bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
c0c2816 temporarily revert the patch due to some conflicts
3019fbb Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM

[tinti]

In fact baabdec commit + Weiming Zhao patch solved the problem at that point. But in the current HEAD the problem is still happening.

[rengolin]

Fixed in r188643

[rengolin]

mentioned in issue llvm/llvm-bugzilla-archive#18926