llvm-objdump for ARM misapplies conditional instruction suffixes to subsequent instructions when an instruction is not recognized #150569
Description
Consider this input code:
.syntax unified
example:
tst r3, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psplim, r2
msr psp, r0
bx r3Assembled with GNU AS:
arm-none-eabi-as -mcpu=cortex-m33 -mfpu=fp-armv8 code.s
If I disassemble with --mcpu=cortex-m33 it works fine:
$ llvm-objdump --mcpu=cortex-m33 -d a.out
a.out: file format elf32-littlearm
Disassembly of section .text:
00000000 <example>:
0: f013 0f10 tst.w r3, #0x10
4: bf08 it eq
6: ecb0 8a10 vldmiaeq r0!, {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
a: f382 880b msr psplim, r2
e: f380 8809 msr psp, r0
12: 4718 bx r3
If I disassemble without any --mcpu option, it doesn't understand the vldmiaeq instruction at 0x6, which is okay (I don't know what the default ARM instruction set is).
But it does something else weird: It erroneously applies the eq suffix to the msr instruction at 0xa:
$ llvm-objdump -d a.out
/usr/local/google/home/jrreinhart/bugs/objdump-iteq/a.out: file format elf32-littlearm
Disassembly of section .text:
00000000 <example>:
0: f013 0f10 tst.w r3, #0x10
4: bf08 it eq
6: ecb0 8a10 <unknown>
a: f382 880b msreq psplim, r2 // not supposed to be `msreq`
e: f380 8809 msr psp, r0
12: 4718 bx r3
and if I force it to Cortex-M3 (which doesn't have PSPLIM), then it moves to the next instruction at 0xe:
llvm-objdump --mcpu=cortex-m3 -d ~/bugs/objdump-iteq/a.out
/usr/local/google/home/jrreinhart/bugs/objdump-iteq/a.out: file format elf32-littlearm
Disassembly of section .text:
00000000 <example>:
0: f013 0f10 tst.w r3, #0x10
4: bf08 it eq
6: ecb0 8a10 <unknown>
a: f382 880b <unknown>
e: f380 8809 msreq psp, r0 // now this instruction got the `eq` suffix
12: 4718 bx r3