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[HLSL] Implement elementwise firstbitlow builtin #116858
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[HLSL] Implement elementwise firstbitlow builtin
V-FEXrt 72f1999
format
V-FEXrt 8434e6a
cleanup
V-FEXrt b6bdc0d
Address comments
V-FEXrt 3c74bfe
cleanup
V-FEXrt a90026c
Divide vectors that surpass 4 element limit
V-FEXrt e67adb9
Address comments
V-FEXrt 7b1a8cc
format
V-FEXrt 742647b
Address comments
V-FEXrt 553335f
Update tests
V-FEXrt 525a662
Address comments
V-FEXrt 08a732a
cleanup
V-FEXrt 2dfcd27
add assert
V-FEXrt 15eaf6e
use iterative approach
V-FEXrt 1325316
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt 242a3c9
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt 2b8d53b
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt 2b8d7f0
Address comments
V-FEXrt 2c0e216
Update llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
V-FEXrt c1b7fad
Address comments
V-FEXrt 64b154a
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt ab3ca85
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt d729dce
Merge branch 'main' into hlsl-firstbitlow
V-FEXrt e37b4bd
Merge branch 'main' into hlsl-firstbitlow
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,153 @@ | ||
| // RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ | ||
| // RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ | ||
| // RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s -DTARGET=dx | ||
| // RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ | ||
| // RUN: spirv-unknown-vulkan-compute %s -fnative-half-type \ | ||
| // RUN: -emit-llvm -disable-llvm-passes \ | ||
| // RUN: -o - | FileCheck %s -DTARGET=spv | ||
|
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||
| #ifdef __HLSL_ENABLE_16_BIT | ||
| // CHECK-LABEL: test_firstbitlow_ushort | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i16 | ||
| uint test_firstbitlow_ushort(uint16_t p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_ushort2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i16 | ||
| uint2 test_firstbitlow_ushort2(uint16_t2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
|
||
| // CHECK-LABEL: test_firstbitlow_ushort3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i16 | ||
| uint3 test_firstbitlow_ushort3(uint16_t3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
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||
| // CHECK-LABEL: test_firstbitlow_ushort4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i16 | ||
| uint4 test_firstbitlow_ushort4(uint16_t4 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
|
||
| // CHECK-LABEL: test_firstbitlow_short | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i16 | ||
| uint test_firstbitlow_short(int16_t p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_short2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i16 | ||
| uint2 test_firstbitlow_short2(int16_t2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_short3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i16 | ||
| uint3 test_firstbitlow_short3(int16_t3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_short4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i16 | ||
| uint4 test_firstbitlow_short4(int16_t4 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
| #endif // __HLSL_ENABLE_16_BIT | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_uint | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i32 | ||
| uint test_firstbitlow_uint(uint p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_uint2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i32 | ||
| uint2 test_firstbitlow_uint2(uint2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_uint3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i32 | ||
| uint3 test_firstbitlow_uint3(uint3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
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||
| // CHECK-LABEL: test_firstbitlow_uint4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i32 | ||
| uint4 test_firstbitlow_uint4(uint4 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_ulong | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i64 | ||
| uint test_firstbitlow_ulong(uint64_t p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_ulong2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i64 | ||
| uint2 test_firstbitlow_ulong2(uint64_t2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
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||
| // CHECK-LABEL: test_firstbitlow_ulong3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i64 | ||
| uint3 test_firstbitlow_ulong3(uint64_t3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_ulong4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i64 | ||
| uint4 test_firstbitlow_ulong4(uint64_t4 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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| // CHECK-LABEL: test_firstbitlow_int | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i32 | ||
| uint test_firstbitlow_int(int p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_int2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i32 | ||
| uint2 test_firstbitlow_int2(int2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_int3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i32 | ||
| uint3 test_firstbitlow_int3(int3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
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||
| // CHECK-LABEL: test_firstbitlow_int4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i32 | ||
| uint4 test_firstbitlow_int4(int4 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_long | ||
| // CHECK: call i32 @llvm.[[TARGET]].firstbitlow.i64 | ||
| uint test_firstbitlow_long(int64_t p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_long2 | ||
| // CHECK: call <2 x i32> @llvm.[[TARGET]].firstbitlow.v2i64 | ||
| uint2 test_firstbitlow_long2(int64_t2 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_long3 | ||
| // CHECK: call <3 x i32> @llvm.[[TARGET]].firstbitlow.v3i64 | ||
| uint3 test_firstbitlow_long3(int64_t3 p0) { | ||
| return firstbitlow(p0); | ||
| } | ||
|
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||
| // CHECK-LABEL: test_firstbitlow_long4 | ||
| // CHECK: call <4 x i32> @llvm.[[TARGET]].firstbitlow.v4i64 | ||
| uint4 test_firstbitlow_long4(int64_t4 p0) { | ||
| return firstbitlow(p0); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| // RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected | ||
|
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||
| int test_too_few_arg() { | ||
| return firstbitlow(); | ||
| // expected-error@-1 {{no matching function for call to 'firstbitlow'}} | ||
| } | ||
|
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||
| int test_too_many_arg(int p0) { | ||
| return firstbitlow(p0, p0); | ||
| // expected-error@-1 {{no matching function for call to 'firstbitlow'}} | ||
| } | ||
|
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||
| double test_int_builtin(double p0) { | ||
| return firstbitlow(p0); | ||
| // expected-error@-1 {{call to 'firstbitlow' is ambiguous}} | ||
| } | ||
|
|
||
| double2 test_int_builtin_2(double2 p0) { | ||
| return __builtin_hlsl_elementwise_firstbitlow(p0); | ||
| // expected-error@-1 {{1st argument must be a vector of integers (was 'double2' (aka 'vector<double, 2>'))}} | ||
| } | ||
|
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||
| float test_int_builtin_3(float p0) { | ||
| return __builtin_hlsl_elementwise_firstbitlow(p0); | ||
| // expected-error@-1 {{1st argument must be a vector of integers (was 'double')}} | ||
| } |
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The test framework doesn't actually assert these lines when split. I had to unsplit them which raised a test failure that was then fixed
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I know you can do a
\continuation for multiple expected directives, but I don't know if you can do that inside the match string. For example I know this works: