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[AMDGPU] Fix DPP combining into V_BITOP3_B32 #153083

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rampitec commented Aug 11, 2025

@rampitec rampitec requested a review from shiltian August 11, 2025 20:55
@rampitec rampitec marked this pull request as ready for review August 11, 2025 20:55
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llvmbot commented Aug 11, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/153083.diff

2 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp (+5)
  • (added) llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir (+18)
diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index f9a907a644373..01270c0036647 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -421,6 +421,11 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
           AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::byte_sel)) {
         DPPInst.addImm(ByteSelOpr->getImm());
       }
+      if (MachineOperand *BitOp3 =
+              TII->getNamedOperand(OrigMI, AMDGPU::OpName::bitop3)) {
+        assert(AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::bitop3));
+        DPPInst.add(*BitOp3);
+      }
     }
     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
     DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir
new file mode 100644
index 0000000000000..9972ec82f63cd
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx1250.mir
@@ -0,0 +1,18 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s -check-prefix=GFX1250
+
+---
+name: v_bitop3_dpp
+tracksRegLiveness: true
+body: |
+  bb.0:
+    ; GFX1250-LABEL: name: v_bitop3_dpp
+    ; GFX1250: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GFX1250-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GFX1250-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], 0, 0, 0, 0, implicit $exec
+    ; GFX1250-NEXT: [[V_BITOP3_B32_e64_dpp:%[0-9]+]]:vgpr_32 = V_BITOP3_B32_e64_dpp [[DEF]], [[V_MOV_B32_e32_]], 1, [[V_MOV_B32_dpp]], 128, 0, 15, 15, 1, implicit $exec
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_dpp %0, %0, 0, 15, 15, 0, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_dpp %0, %0, 0, 0, 0, 0, implicit $exec
+    %3:vgpr_32 = V_BITOP3_B32_e64 %1, 1, %2, 128, implicit $exec
+...

@rampitec rampitec force-pushed the users/rampitec/08-11-_amdgpu_fix_dpp_combining_into_v_bitop3_b32 branch from 748ffba to 6d75580 Compare August 11, 2025 22:07
@rampitec rampitec merged commit b9ecee9 into main Aug 11, 2025
9 checks passed
@rampitec rampitec deleted the users/rampitec/08-11-_amdgpu_fix_dpp_combining_into_v_bitop3_b32 branch August 11, 2025 22:39
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