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Sep 19, 2023
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AMDGPU: Fix handling of -0 in round lowering #65761

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20 changes: 11 additions & 9 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Expand Up @@ -6575,23 +6575,25 @@ LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
// round(x) =>
// t = trunc(x);
// d = fabs(x - t);
// o = copysign(1.0f, x);
// return t + (d >= 0.5 ? o : 0.0);
// o = copysign(d >= 0.5 ? 1.0 : 0.0, x);
// return t + o;

auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags);

auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags);
auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags);
auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
auto One = MIRBuilder.buildFConstant(Ty, 1.0);

auto Half = MIRBuilder.buildFConstant(Ty, 0.5);
auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X);
auto Cmp =
MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, Flags);

auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half,
Flags);
auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags);
// Could emit G_UITOFP instead
auto One = MIRBuilder.buildFConstant(Ty, 1.0);
auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
auto BoolFP = MIRBuilder.buildSelect(Ty, Cmp, One, Zero);
auto SignedOffset = MIRBuilder.buildFCopysign(Ty, BoolFP, X);

MIRBuilder.buildFAdd(DstReg, T, Sel, Flags);
MIRBuilder.buildFAdd(DstReg, T, SignedOffset, Flags);

MI.eraseFromParent();
return Legalized;
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10 changes: 4 additions & 6 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Expand Up @@ -2429,18 +2429,16 @@ SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {

const SDValue Zero = DAG.getConstantFP(0.0, SL, VT);
const SDValue One = DAG.getConstantFP(1.0, SL, VT);
const SDValue Half = DAG.getConstantFP(0.5, SL, VT);

SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);

EVT SetCCVT =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);

const SDValue Half = DAG.getConstantFP(0.5, SL, VT);
SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero);

SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);

return DAG.getNode(ISD::FADD, SL, VT, T, Sel);
SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X);
return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset);
}

SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
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858 changes: 477 additions & 381 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
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81 changes: 40 additions & 41 deletions llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
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Expand Up @@ -3794,85 +3794,84 @@ define half @v_fneg_round_f16(half %a) #0 {
; SI-SAFE: ; %bb.0:
; SI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-SAFE-NEXT: s_brev_b32 s4, -2
; SI-SAFE-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-SAFE-NEXT: v_trunc_f32_e32 v2, v0
; SI-SAFE-NEXT: v_bfi_b32 v1, s4, 1.0, v0
; SI-SAFE-NEXT: v_sub_f32_e32 v0, v0, v2
; SI-SAFE-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
; SI-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SAFE-NEXT: v_add_f32_e32 v0, v2, v0
; SI-SAFE-NEXT: v_trunc_f32_e32 v1, v0
; SI-SAFE-NEXT: v_sub_f32_e32 v2, v0, v1
; SI-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
; SI-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
; SI-SAFE-NEXT: s_brev_b32 s4, -2
; SI-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
; SI-SAFE-NEXT: v_add_f32_e32 v0, v1, v0
; SI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; SI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; SI-NSZ-LABEL: v_fneg_round_f16:
; SI-NSZ: ; %bb.0:
; SI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NSZ-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NSZ-NEXT: s_brev_b32 s4, -2
; SI-NSZ-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NSZ-NEXT: v_trunc_f32_e32 v2, v0
; SI-NSZ-NEXT: v_bfi_b32 v1, s4, 1.0, v0
; SI-NSZ-NEXT: v_sub_f32_e32 v0, v0, v2
; SI-NSZ-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
; SI-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-NSZ-NEXT: v_sub_f32_e64 v0, -v2, v0
; SI-NSZ-NEXT: v_trunc_f32_e32 v1, v0
; SI-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
; SI-NSZ-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
; SI-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
; SI-NSZ-NEXT: s_brev_b32 s4, -2
; SI-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
; SI-NSZ-NEXT: v_sub_f32_e64 v0, -v1, v0
; SI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; VI-SAFE-LABEL: v_fneg_round_f16:
; VI-SAFE: ; %bb.0:
; VI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SAFE-NEXT: v_trunc_f16_e32 v1, v0
; VI-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
; VI-SAFE-NEXT: v_mov_b32_e32 v3, 0x3c00
; VI-SAFE-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
; VI-SAFE-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; VI-SAFE-NEXT: s_movk_i32 s4, 0x7fff
; VI-SAFE-NEXT: v_mov_b32_e32 v1, 0x3c00
; VI-SAFE-NEXT: v_trunc_f16_e32 v2, v0
; VI-SAFE-NEXT: v_bfi_b32 v1, s4, v1, v0
; VI-SAFE-NEXT: v_sub_f16_e32 v0, v0, v2
; VI-SAFE-NEXT: v_cmp_ge_f16_e64 vcc, |v0|, 0.5
; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SAFE-NEXT: v_add_f16_e32 v0, v2, v0
; VI-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
; VI-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; VI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; VI-NSZ-LABEL: v_fneg_round_f16:
; VI-NSZ: ; %bb.0:
; VI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NSZ-NEXT: v_trunc_f16_e32 v1, v0
; VI-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
; VI-NSZ-NEXT: v_mov_b32_e32 v3, 0x3c00
; VI-NSZ-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
; VI-NSZ-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
; VI-NSZ-NEXT: s_movk_i32 s4, 0x7fff
; VI-NSZ-NEXT: v_mov_b32_e32 v1, 0x3c00
; VI-NSZ-NEXT: v_trunc_f16_e32 v2, v0
; VI-NSZ-NEXT: v_bfi_b32 v1, s4, v1, v0
; VI-NSZ-NEXT: v_sub_f16_e32 v0, v0, v2
; VI-NSZ-NEXT: v_cmp_ge_f16_e64 vcc, |v0|, 0.5
; VI-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v2, v0
; VI-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
; VI-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
; VI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SAFE-LABEL: v_fneg_round_f16:
; GFX11-SAFE: ; %bb.0:
; GFX11-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SAFE-NEXT: v_trunc_f16_e32 v1, v0
; GFX11-SAFE-NEXT: s_movk_i32 s0, 0x3c00
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SAFE-NEXT: v_sub_f16_e32 v2, v0, v1
; GFX11-SAFE-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
; GFX11-SAFE-NEXT: v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX11-SAFE-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
; GFX11-SAFE-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SAFE-NEXT: v_add_f16_e32 v0, v1, v0
; GFX11-SAFE-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SAFE-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX11-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-NSZ-LABEL: v_fneg_round_f16:
; GFX11-NSZ: ; %bb.0:
; GFX11-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NSZ-NEXT: v_trunc_f16_e32 v1, v0
; GFX11-NSZ-NEXT: s_movk_i32 s0, 0x3c00
; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NSZ-NEXT: v_sub_f16_e32 v2, v0, v1
; GFX11-NSZ-NEXT: v_bfi_b32 v0, 0x7fff, s0, v0
; GFX11-NSZ-NEXT: v_cmp_ge_f16_e64 vcc_lo, |v2|, 0.5
; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo
; GFX11-NSZ-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
; GFX11-NSZ-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
; GFX11-NSZ-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NSZ-NEXT: v_sub_f16_e64 v0, -v1, v0
; GFX11-NSZ-NEXT: s_setpc_b64 s[30:31]
%round = call half @llvm.round.f16(half %a)
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24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
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Expand Up @@ -2207,26 +2207,26 @@ define float @v_fneg_round_f32(float %a) #0 {
; GCN-SAFE-LABEL: v_fneg_round_f32:
; GCN-SAFE: ; %bb.0:
; GCN-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SAFE-NEXT: v_trunc_f32_e32 v1, v0
; GCN-SAFE-NEXT: v_sub_f32_e32 v2, v0, v1
; GCN-SAFE-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
; GCN-SAFE-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
; GCN-SAFE-NEXT: s_brev_b32 s4, -2
; GCN-SAFE-NEXT: v_trunc_f32_e32 v2, v0
; GCN-SAFE-NEXT: v_bfi_b32 v1, s4, 1.0, v0
; GCN-SAFE-NEXT: v_sub_f32_e32 v0, v0, v2
; GCN-SAFE-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
; GCN-SAFE-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GCN-SAFE-NEXT: v_add_f32_e32 v0, v2, v0
; GCN-SAFE-NEXT: v_bfi_b32 v0, s4, v2, v0
; GCN-SAFE-NEXT: v_add_f32_e32 v0, v1, v0
; GCN-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
; GCN-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; GCN-NSZ-LABEL: v_fneg_round_f32:
; GCN-NSZ: ; %bb.0:
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NSZ-NEXT: v_trunc_f32_e32 v1, v0
; GCN-NSZ-NEXT: v_sub_f32_e32 v2, v0, v1
; GCN-NSZ-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
; GCN-NSZ-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
; GCN-NSZ-NEXT: s_brev_b32 s4, -2
; GCN-NSZ-NEXT: v_trunc_f32_e32 v2, v0
; GCN-NSZ-NEXT: v_bfi_b32 v1, s4, 1.0, v0
; GCN-NSZ-NEXT: v_sub_f32_e32 v0, v0, v2
; GCN-NSZ-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
; GCN-NSZ-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v2, v0
; GCN-NSZ-NEXT: v_bfi_b32 v0, s4, v2, v0
; GCN-NSZ-NEXT: v_sub_f32_e64 v0, -v1, v0
; GCN-NSZ-NEXT: s_setpc_b64 s[30:31]
%round = call float @llvm.round.f32(float %a)
%fneg = fneg float %round
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/known-never-snan.ll
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Expand Up @@ -455,13 +455,13 @@ define float @v_test_known_not_snan_round_input_fmed3_r_i_i_f32(float %a) #0 {
; GCN-LABEL: v_test_known_not_snan_round_input_fmed3_r_i_i_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_trunc_f32_e32 v1, v0
; GCN-NEXT: v_sub_f32_e32 v2, v0, v1
; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, 0.5
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, 1.0, s[4:5]
; GCN-NEXT: s_brev_b32 s4, -2
; GCN-NEXT: v_trunc_f32_e32 v2, v0
; GCN-NEXT: v_bfi_b32 v1, s4, 1.0, v0
; GCN-NEXT: v_sub_f32_e32 v0, v0, v2
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, 0.5
; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GCN-NEXT: v_add_f32_e32 v0, v2, v0
; GCN-NEXT: v_bfi_b32 v0, s4, v2, v0
; GCN-NEXT: v_add_f32_e32 v0, v1, v0
; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GCN-NEXT: s_setpc_b64 s[30:31]
%known.not.snan = call float @llvm.round.f32(float %a)
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