Swedev 414443

llvm/include/llvm/CodeGen/TargetInstrInfo.h

@@ -140,6 +140,15 @@ class TargetInstrInfo : public MCInstrInfo {
     return false;
   }
 
+  /// Attempting to move \p MoveCandidate after \p ModifierInstr .
+  /// \p MoveCandidate uses \p Reg but \p ModifierInstr redefines \p Reg.
+  /// Let target check it redefines it using same value.
+  virtual bool
+  modifiesRegisterImplicitly(Register Reg, const MachineInstr *MoveCandidate,
+                             const MachineInstr *ModifierInstr) const {
+    return true;
+  }
+
 protected:
   /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
   /// set, this hook lets the target specify whether the instruction is actually

llvm/lib/CodeGen/MachineSink.cpp

@@ -290,8 +290,10 @@ static bool blockPrologueInterferes(const MachineBasicBlock *BB,
       if (MO.isUse()) {
         if (Reg.isPhysical() && MRI && MRI->isConstantPhysReg(Reg))
           continue;
-        if (PI->modifiesRegister(Reg, TRI))
+        if (PI->modifiesRegister(Reg, TRI) &&
+            TII->modifiesRegisterImplicitly(Reg, &MI, &*PI)) {
           return true;
+        }
       } else {
         if (PI->readsRegister(Reg, TRI))
           return true;

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -171,6 +171,39 @@ bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
          isVALU(*MO.getParent()) && !resultDependsOnExec(*MO.getParent());
 }
 
+bool SIInstrInfo::modifiesRegisterImplicitly(
+    Register Reg, const MachineInstr *MoveCandidate,
+    const MachineInstr *ModifierInstr) const {
+
+  if (ModifierInstr->getOpcode() == AMDGPU::SI_END_CF && Reg == AMDGPU::EXEC) {
+    const MachineRegisterInfo &MRI = MoveCandidate->getMF()->getRegInfo();
+
+    // Looking if this is a simple case of:
+    //
+    //  %0 = MoveCandidate %1, %2, implicit $exec
+    //  %EndCF:sreg_64 = SI_IF %cond, %bb.B
+    //  S_BRANCH %bb.A
+    //
+    // bb.A
+    //  ...
+    //
+    // bb.B
+    //  SI_END_CF %EndCF, implicit-def dead $exec
+    //  ... MoveCandidate should be moved here
+
+    // MoveCandidate is from block that started divergent control flow via SI_IF
+    // it is a simple SI_IF (no loops) - only user of SI_IF is SI_END_CF
+    // SI_END_CF restores exec mask as it was before SI_IF (unchanged)
+    Register EndCF = ModifierInstr->getOperand(0).getReg();
+    MachineInstr *SIIF = MRI.getVRegDef(EndCF);
+    if (SIIF->getOpcode() == AMDGPU::SI_IF && MRI.hasOneUse(EndCF) &&
+        SIIF->getParent() == MoveCandidate->getParent())
+      return false;
+  }
+
+  return true;
+}
+
 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
                                           int64_t &Offset0,
                                           int64_t &Offset1) const {

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -222,6 +222,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   bool isIgnorableUse(const MachineOperand &MO) const override;
 
+  bool
+  modifiesRegisterImplicitly(Register Reg, const MachineInstr *MoveCandidate,
+                             const MachineInstr *ModifierInstr) const override;
+
   bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
                                int64_t &Offset1) const override;