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[RISCV] Fix bugs about getting register list of Zcmp push/pop. #66073

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Merged
yetingk merged 5 commits into from
Sep 20, 2023
Merged

[RISCV] Fix bugs about getting register list of Zcmp push/pop. #66073

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bf518a6
[RISCV] Fix internal compiler about Zcmp.
Sep 12, 2023
170908a
[RISCV] Use right pushed register number when max pushed register is …
Sep 14, 2023
2df605c
[RISCV] Preserve original test which check case only using s4.
Sep 15, 2023
9f8d8d5
[RISCV] Update comments.
Sep 15, 2023
44dc55f
[RISCV] Update test to not use inline asm and rename zcmp-crash.ll to…
Sep 18, 2023
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37 changes: 18 additions & 19 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -228,35 +228,36 @@ getRestoreLibCallName(const MachineFunction &MF,

// Return encoded value for PUSH/POP instruction, representing
// registers to store/load.
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@kito-cheng kito-cheng Sep 14, 2023

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Comment need to update to reflect the update.

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@yetingk yetingk Sep 15, 2023

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Done.

static unsigned getPushPopEncoding(const Register MaxReg) {
static std::pair<unsigned, unsigned>
getPushPopEncodingAndNum(const Register MaxReg) {
switch (MaxReg) {
default:
llvm_unreachable("Unexpected Reg for Push/Pop Inst");
case RISCV::X27: /*s11*/
case RISCV::X26: /*s10*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S11;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S11, 13);
case RISCV::X25: /*s9*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S9;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S9, 11);
case RISCV::X24: /*s8*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S8;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S8, 10);
case RISCV::X23: /*s7*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S7;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S7, 9);
case RISCV::X22: /*s6*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S6;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S6, 8);
case RISCV::X21: /*s5*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S5;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S5, 7);
case RISCV::X20: /*s4*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S4;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S4, 6);
case RISCV::X19: /*s3*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S3;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S3, 5);
case RISCV::X18: /*s2*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S2;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S2, 4);
case RISCV::X9: /*s1*/
return llvm::RISCVZC::RLISTENCODE::RA_S0_S1;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S1, 3);
case RISCV::X8: /*s0*/
return llvm::RISCVZC::RLISTENCODE::RA_S0;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0, 2);
case RISCV::X1: /*ra*/
return llvm::RISCVZC::RLISTENCODE::RA;
return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA, 1);
}
}

Expand Down Expand Up @@ -1371,14 +1372,12 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (RVFI->isPushable(*MF)) {
Register MaxReg = getMaxPushPopReg(*MF, CSI);
unsigned PushedRegNum =
getPushPopEncoding(MaxReg) - llvm::RISCVZC::RLISTENCODE::RA + 1;
RVFI->setRVPushRegs(PushedRegNum);
RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));

if (MaxReg != RISCV::NoRegister) {
auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
RVFI->setRVPushRegs(PushedRegNum);
RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));

// Use encoded number to represent registers to spill.
unsigned RegEnc = getPushPopEncoding(MaxReg);
RVFI->setRVPushRlist(RegEnc);
MachineInstrBuilder PushBuilder =
BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))
Expand Down
70 changes: 35 additions & 35 deletions llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1998,12 +1998,12 @@ define void @foo() {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset s4, -4
; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset s11, -4
; RV32I-NEXT: #APP
; RV32I-NEXT: li s4, 0
; RV32I-NEXT: li s11, 0
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -2013,62 +2013,62 @@ define void @foo() {
; RV32I-WITH-FP-NEXT: .cfi_def_cfa_offset 16
; RV32I-WITH-FP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s4, 4(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s11, 4(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: .cfi_offset ra, -4
; RV32I-WITH-FP-NEXT: .cfi_offset s0, -8
; RV32I-WITH-FP-NEXT: .cfi_offset s4, -12
; RV32I-WITH-FP-NEXT: .cfi_offset s11, -12
; RV32I-WITH-FP-NEXT: addi s0, sp, 16
; RV32I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32I-WITH-FP-NEXT: #APP
; RV32I-WITH-FP-NEXT: li s4, 0
; RV32I-WITH-FP-NEXT: li s11, 0
; RV32I-WITH-FP-NEXT: #NO_APP
; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: addi sp, sp, 16
; RV32I-WITH-FP-NEXT: ret
;
; RV32IZCMP-LABEL: foo:
; RV32IZCMP: # %bb.0: # %entry
; RV32IZCMP-NEXT: cm.push {ra, s0-s4}, -32
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 32
; RV32IZCMP-NEXT: .cfi_offset s4, -4
; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -64
; RV32IZCMP-NEXT: .cfi_def_cfa_offset 64
; RV32IZCMP-NEXT: .cfi_offset s11, -4
; RV32IZCMP-NEXT: #APP
; RV32IZCMP-NEXT: li s4, 0
; RV32IZCMP-NEXT: li s11, 0
; RV32IZCMP-NEXT: #NO_APP
; RV32IZCMP-NEXT: cm.popret {ra, s0-s4}, 32
; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 64
;
; RV32IZCMP-WITH-FP-LABEL: foo:
; RV32IZCMP-WITH-FP: # %bb.0: # %entry
; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, -16
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 16
; RV32IZCMP-WITH-FP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: sw s4, 4(sp) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: sw s11, 4(sp) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset ra, -4
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s0, -8
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s4, -12
; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s11, -12
; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 16
; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IZCMP-WITH-FP-NEXT: #APP
; RV32IZCMP-WITH-FP-NEXT: li s4, 0
; RV32IZCMP-WITH-FP-NEXT: li s11, 0
; RV32IZCMP-WITH-FP-NEXT: #NO_APP
; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 16
; RV32IZCMP-WITH-FP-NEXT: ret
;
; RV64I-LABEL: foo:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: .cfi_def_cfa_offset 16
; RV64I-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset s4, -8
; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset s11, -8
; RV64I-NEXT: #APP
; RV64I-NEXT: li s4, 0
; RV64I-NEXT: li s11, 0
; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand All @@ -2078,53 +2078,53 @@ define void @foo() {
; RV64I-WITH-FP-NEXT: .cfi_def_cfa_offset 32
; RV64I-WITH-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: .cfi_offset ra, -8
; RV64I-WITH-FP-NEXT: .cfi_offset s0, -16
; RV64I-WITH-FP-NEXT: .cfi_offset s4, -24
; RV64I-WITH-FP-NEXT: .cfi_offset s11, -24
; RV64I-WITH-FP-NEXT: addi s0, sp, 32
; RV64I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64I-WITH-FP-NEXT: #APP
; RV64I-WITH-FP-NEXT: li s4, 0
; RV64I-WITH-FP-NEXT: li s11, 0
; RV64I-WITH-FP-NEXT: #NO_APP
; RV64I-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: addi sp, sp, 32
; RV64I-WITH-FP-NEXT: ret
;
; RV64IZCMP-LABEL: foo:
; RV64IZCMP: # %bb.0: # %entry
; RV64IZCMP-NEXT: cm.push {ra, s0-s4}, -48
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 48
; RV64IZCMP-NEXT: .cfi_offset s4, -8
; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -112
; RV64IZCMP-NEXT: .cfi_def_cfa_offset 112
; RV64IZCMP-NEXT: .cfi_offset s11, -8
; RV64IZCMP-NEXT: #APP
; RV64IZCMP-NEXT: li s4, 0
; RV64IZCMP-NEXT: li s11, 0
; RV64IZCMP-NEXT: #NO_APP
; RV64IZCMP-NEXT: cm.popret {ra, s0-s4}, 48
; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 112
;
; RV64IZCMP-WITH-FP-LABEL: foo:
; RV64IZCMP-WITH-FP: # %bb.0: # %entry
; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, -32
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 32
; RV64IZCMP-WITH-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: sd s4, 8(sp) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset ra, -8
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s0, -16
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s4, -24
; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s11, -24
; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 32
; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IZCMP-WITH-FP-NEXT: #APP
; RV64IZCMP-WITH-FP-NEXT: li s4, 0
; RV64IZCMP-WITH-FP-NEXT: li s11, 0
; RV64IZCMP-WITH-FP-NEXT: #NO_APP
; RV64IZCMP-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 32
; RV64IZCMP-WITH-FP-NEXT: ret
entry:
tail call void asm sideeffect "li s4, 0", "~{s4}"()
tail call void asm sideeffect "li s11, 0", "~{s11}"()
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@kito-cheng kito-cheng Sep 14, 2023

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Add one more function instead of updating this?

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@yetingk yetingk Sep 15, 2023

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Done.

ret void
}

Expand Down
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/RISCV/zcmp-crash.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+f,+zcmp -verify-machineinstrs < %s | FileCheck %s

; Test the file could be compiled successfully.
define void @bar() {
; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: .cfi_offset fs0, -4
; CHECK-NEXT: #APP
; CHECK-NEXT: fmv.w.x fs0, zero
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
entry:
tail call void asm sideeffect "fmv.w.x fs0, zero", "~{fs0}"()
ret void
}