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[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad #67014

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Merged
wangpc-pp merged 3 commits into from
Sep 22, 2023
Merged

[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value of PseudoFloatLoad #67014

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b944890
[RISCV][NFC] Remove rdty arg of PseudoLoad and the default rdty value…
wangpc-pp Sep 21, 2023
81aa9e9
Update RISCVInstrFormats.td
wangpc-pp Sep 21, 2023
7933a32
Update RISCVInstrInfo.td
wangpc-pp Sep 21, 2023
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6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -241,16 +241,16 @@ class PseudoQuietFCMP<DAGOperand Ty>
}

// Pseudo load instructions.
class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
: Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
class PseudoIntLoad<string opcodestr>
: Pseudo<(outs GPR:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
let hasSideEffects = 0;
let mayLoad = 1;
let mayStore = 0;
let isCodeGenOnly = 0;
let isAsmParserOnly = 1;
}

class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
class PseudoFloatLoad<string opcodestr, RegisterClass rdty>
: Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
let hasSideEffects = 0;
let mayLoad = 1;
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14 changes: 7 additions & 7 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -920,19 +920,19 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [],
"li", "$rd, $imm">;

def PseudoLB : PseudoLoad<"lb">;
def PseudoLBU : PseudoLoad<"lbu">;
def PseudoLH : PseudoLoad<"lh">;
def PseudoLHU : PseudoLoad<"lhu">;
def PseudoLW : PseudoLoad<"lw">;
def PseudoLB : PseudoIntLoad<"lb">;
def PseudoLBU : PseudoIntLoad<"lbu">;
def PseudoLH : PseudoIntLoad<"lh">;
def PseudoLHU : PseudoIntLoad<"lhu">;
def PseudoLW : PseudoIntLoad<"lw">;

def PseudoSB : PseudoStore<"sb">;
def PseudoSH : PseudoStore<"sh">;
def PseudoSW : PseudoStore<"sw">;

let Predicates = [IsRV64] in {
def PseudoLWU : PseudoLoad<"lwu">;
def PseudoLD : PseudoLoad<"ld">;
def PseudoLWU : PseudoIntLoad<"lwu">;
def PseudoLD : PseudoIntLoad<"ld">;
def PseudoSD : PseudoStore<"sd">;
} // Predicates = [IsRV64]

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