Skip to content

AMDGPU: Teach isArgPassedInSGPR() about cs_chain* calling convention #67086

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
ruiling merged 1 commit into from
Sep 22, 2023
Merged

AMDGPU: Teach isArgPassedInSGPR() about cs_chain* calling convention #67086

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2531,6 +2531,8 @@ bool isArgPassedInSGPR(const Argument *A) {
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_Gfx:
case CallingConv::AMDGPU_CS_Chain:
case CallingConv::AMDGPU_CS_ChainPreserve:
// For non-compute shaders, SGPR inputs are marked with either inreg or
// byval. Everything else is in VGPRs.
return A->hasAttribute(Attribute::InReg) ||
Expand All @@ -2556,6 +2558,8 @@ bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo) {
case CallingConv::AMDGPU_PS:
case CallingConv::AMDGPU_CS:
case CallingConv::AMDGPU_Gfx:
case CallingConv::AMDGPU_CS_Chain:
case CallingConv::AMDGPU_CS_ChainPreserve:
// For non-compute shaders, SGPR inputs are marked with either inreg or
// byval. Everything else is in VGPRs.
return CB->paramHasAttr(ArgNo, Attribute::InReg) ||
Expand Down
21 changes: 21 additions & 0 deletions llvm/test/Analysis/UniformityAnalysis/AMDGPU/kernel-args.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -36,4 +36,25 @@ define void @test_c(ptr addrspace(5) byval([4 x <16 x i8>]) %arg0, float inreg %
ret void
}

; CHECK-LABEL: for function 'test_amdgpu_cs_chain':
; CHECK-DAG: DIVERGENT: ptr addrspace(4) %arg0
; CHECK-DAG: DIVERGENT: <2 x i32> %arg3
; CHECK-DAG: DIVERGENT: <3 x i32> %arg4
; CHECK-DAG: DIVERGENT: float %arg5
; CHECK-DAG: DIVERGENT: i32 %arg6
; CHECK-NOT: DIVERGENT
define amdgpu_cs_chain void @test_amdgpu_cs_chain(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
ret void
}

; CHECK-LABEL: for function 'test_amdgpu_cs_chain_preserve':
; CHECK-DAG: DIVERGENT: ptr addrspace(4) %arg0
; CHECK-DAG: DIVERGENT: <2 x i32> %arg3
; CHECK-DAG: DIVERGENT: <3 x i32> %arg4
; CHECK-DAG: DIVERGENT: float %arg5
; CHECK-DAG: DIVERGENT: i32 %arg6
; CHECK-NOT: DIVERGENT
define amdgpu_cs_chain_preserve void @test_amdgpu_cs_chain_preserve(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
ret void
}
attributes #0 = { nounwind }