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Merged
preames merged 3 commits into from
Oct 6, 2023
Merged

[RISCV] Strip W suffix from ADDIW #68425

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0606f00
[RISCV] Strip W suffix from ADDIW, SRLIW, and SRAIW
preames Oct 6, 2023
3ac5a4c
Back out unsound shift changes
preames Oct 6, 2023
fd4f5cd
Rework comment to clarify/correct
preames Oct 6, 2023
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14 changes: 9 additions & 5 deletions llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
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Expand Up @@ -12,11 +12,12 @@
// extended bits aren't consumed or because the input was already sign extended
// by an earlier instruction.
//
// Then it removes the -w suffix from addw, slliw and mulw instructions
// whenever all users are dependent only on the lower word of the result of the
// instruction. We do this only for addw, slliw, and mulw because the -w forms
// are less compressible: c.add and c.slli have a larger register encoding than
// their w counterparts, and there's no compressible version of mulw.

@topperc topperc Oct 6, 2023

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This comment was incorrect. c.mul was added with Zcb.

// Then it removes the -w suffix from opw instructions whenever all users are
// dependent only on the lower word of the result of the instruction. This is
// profitable for addw because c.add has a larger register encoding than c.addw.
// For the remaining opw instructions, there is no compressed w variant. This

@topperc topperc Oct 6, 2023

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There is a c.addiw.

C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. C.ADDIW is only valid when rd̸=x0; the code points with rd=x0 are reserved.

@preames preames Oct 6, 2023

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Agreed, need to fix comment.

// tramsform also has the side effect of making RV32 and RV64 codegen for 32
// bit constants match which helps reduce check duplication in LIT tests.
//
//===---------------------------------------------------------------------===//

Expand Down Expand Up @@ -661,8 +662,11 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
default:
continue;
case RISCV::ADDW: Opc = RISCV::ADD; break;
case RISCV::ADDIW: Opc = RISCV::ADDI; break;
case RISCV::MULW: Opc = RISCV::MUL; break;
case RISCV::SLLIW: Opc = RISCV::SLLI; break;
case RISCV::SRLIW: Opc = RISCV::SRLI; break;
case RISCV::SRAIW: Opc = RISCV::SRAI; break;
}

if (hasAllWUsers(MI, ST, MRI)) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Expand Up @@ -34,9 +34,9 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
; RV64IM-LABEL: add_i8_signext_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: slli a0, a0, 24
; RV64IM-NEXT: sraiw a0, a0, 24
; RV64IM-NEXT: srai a0, a0, 24
; RV64IM-NEXT: slli a1, a1, 24
; RV64IM-NEXT: sraiw a1, a1, 24
; RV64IM-NEXT: srai a1, a1, 24
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
entry:
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/add-before-shl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
;
; RV64I-LABEL: add_small_const:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: jalr zero, 0(ra)
Expand All @@ -39,7 +39,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
;
; RV64C-LABEL: add_small_const:
; RV64C: # %bb.0:
; RV64C-NEXT: c.addiw a0, 1
; RV64C-NEXT: c.addi a0, 1
; RV64C-NEXT: c.slli a0, 56
; RV64C-NEXT: c.srai a0, 56
; RV64C-NEXT: c.jr ra
Expand Down Expand Up @@ -78,7 +78,7 @@ define signext i32 @add_large_const(i32 signext %a) nounwind {
; RV64C-LABEL: add_large_const:
; RV64C: # %bb.0:
; RV64C-NEXT: c.lui a1, 1
; RV64C-NEXT: c.addiw a1, -1
; RV64C-NEXT: c.addi a1, -1
; RV64C-NEXT: c.add a0, a1
; RV64C-NEXT: c.slli a0, 48
; RV64C-NEXT: c.srai a0, 48
Expand Down Expand Up @@ -118,7 +118,7 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
; RV64C-LABEL: add_huge_const:
; RV64C: # %bb.0:
; RV64C-NEXT: c.lui a1, 8
; RV64C-NEXT: c.addiw a1, -1
; RV64C-NEXT: c.addi a1, -1
; RV64C-NEXT: c.add a0, a1
; RV64C-NEXT: c.slli a0, 48
; RV64C-NEXT: c.srai a0, 48
Expand All @@ -139,7 +139,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
;
; RV64I-LABEL: add_non_machine_type:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 256
; RV64I-NEXT: addi a0, a0, 256
; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: srai a0, a0, 40
; RV64I-NEXT: jalr zero, 0(ra)
Expand All @@ -153,7 +153,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
;
; RV64C-LABEL: add_non_machine_type:
; RV64C: # %bb.0:
; RV64C-NEXT: addiw a0, a0, 256
; RV64C-NEXT: addi a0, a0, 256
; RV64C-NEXT: c.slli a0, 52
; RV64C-NEXT: c.srai a0, 40
; RV64C-NEXT: c.jr ra
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/add-imm.ll
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Expand Up @@ -29,7 +29,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_low_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 2048
Expand All @@ -45,7 +45,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_high_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 4094
Expand All @@ -63,7 +63,7 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
; RV64I-LABEL: add_positive_high_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, 4095
Expand Down Expand Up @@ -93,7 +93,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_high_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: ret
%1 = add i32 %a, -2049
Expand All @@ -109,7 +109,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_low_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -4096
Expand All @@ -127,7 +127,7 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
; RV64I-LABEL: add_negative_low_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, -4097
Expand All @@ -143,7 +143,7 @@ define i32 @add32_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add32_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 952
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
Expand All @@ -159,7 +159,7 @@ define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
;
; RV64I-LABEL: add32_sext_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 952
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
Expand All @@ -178,7 +178,7 @@ define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {
;
; RV64I-LABEL: add32_sext_reject_on_rv64:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 953
; RV64I-NEXT: lui a1, %hi(gv0)
; RV64I-NEXT: sw a0, %lo(gv0)(a1)
Expand Down Expand Up @@ -231,7 +231,7 @@ define void @add32_reject() nounwind {
; RV64I-NEXT: lui a2, %hi(gb)
; RV64I-NEXT: lw a3, %lo(gb)(a2)
; RV64I-NEXT: lui a4, 1
; RV64I-NEXT: addiw a4, a4, -1096
; RV64I-NEXT: addi a4, a4, -1096
; RV64I-NEXT: add a1, a1, a4
; RV64I-NEXT: add a3, a3, a4
; RV64I-NEXT: sw a1, %lo(ga)(a0)
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/addimm-mulimm.ll
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Expand Up @@ -84,7 +84,7 @@ define i32 @add_mul_combine_accept_b1(i32 %x) {
; RV64IMB-NEXT: li a1, 23
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: addi a1, a1, 1119
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 8953
Expand All @@ -107,7 +107,7 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
; RV64IMB-NEXT: li a1, 23
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 50
; RV64IMB-NEXT: addiw a1, a1, 1119
; RV64IMB-NEXT: addi a1, a1, 1119
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = add i32 %x, 8953
Expand Down Expand Up @@ -153,7 +153,7 @@ define i32 @add_mul_combine_reject_a1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_a1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
Expand All @@ -172,7 +172,7 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_a2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -217,7 +217,7 @@ define i32 @add_mul_combine_reject_c1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_c1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1000
; RV64IMB-NEXT: addi a0, a0, 1000
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: sext.w a0, a0
Expand All @@ -237,7 +237,7 @@ define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_c2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1000
; RV64IMB-NEXT: addi a0, a0, 1000
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: sext.w a0, a0
Expand Down Expand Up @@ -349,7 +349,7 @@ define i32 @add_mul_combine_reject_e1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_e1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
Expand All @@ -368,7 +368,7 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_e2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1971
; RV64IMB-NEXT: addi a0, a0, 1971
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -414,7 +414,7 @@ define i32 @add_mul_combine_reject_f1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_f1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1972
; RV64IMB-NEXT: addi a0, a0, 1972
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 11
Expand All @@ -435,7 +435,7 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_f2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 1972
; RV64IMB-NEXT: addi a0, a0, 1972
; RV64IMB-NEXT: li a1, 29
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 11
Expand Down Expand Up @@ -483,7 +483,7 @@ define i32 @add_mul_combine_reject_g1(i32 %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_g1:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 100
; RV64IMB-NEXT: addi a0, a0, 100
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: addiw a0, a0, 10
Expand All @@ -504,7 +504,7 @@ define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
;
; RV64IMB-LABEL: add_mul_combine_reject_g2:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 100
; RV64IMB-NEXT: addi a0, a0, 100
; RV64IMB-NEXT: sh3add a1, a0, a0
; RV64IMB-NEXT: sh3add a0, a1, a0
; RV64IMB-NEXT: addiw a0, a0, 10
Expand Down Expand Up @@ -581,9 +581,9 @@ define i32 @mul3000_add8990_a(i32 %x) {
;
; RV64IMB-LABEL: mul3000_add8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 3
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, -10
; RV64IMB-NEXT: ret
Expand All @@ -604,9 +604,9 @@ define signext i32 @mul3000_add8990_b(i32 signext %x) {
;
; RV64IMB-LABEL: mul3000_add8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 3
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, -10
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -656,9 +656,9 @@ define i32 @mul3000_sub8990_a(i32 %x) {
;
; RV64IMB-LABEL: mul3000_sub8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, -3
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 10
; RV64IMB-NEXT: ret
Expand All @@ -679,9 +679,9 @@ define signext i32 @mul3000_sub8990_b(i32 signext %x) {
;
; RV64IMB-LABEL: mul3000_sub8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, -3
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: addi a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 10
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -732,9 +732,9 @@ define i32 @mulneg3000_add8990_a(i32 %x) {
;
; RV64IMB-LABEL: mulneg3000_add8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, -3
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, -10
; RV64IMB-NEXT: ret
Expand All @@ -755,9 +755,9 @@ define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
;
; RV64IMB-LABEL: mulneg3000_add8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, -3
; RV64IMB-NEXT: addi a0, a0, -3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, -10
; RV64IMB-NEXT: ret
Expand Down Expand Up @@ -808,9 +808,9 @@ define i32 @mulneg3000_sub8990_a(i32 %x) {
;
; RV64IMB-LABEL: mulneg3000_sub8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 3
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 10
; RV64IMB-NEXT: ret
Expand All @@ -831,9 +831,9 @@ define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
;
; RV64IMB-LABEL: mulneg3000_sub8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: addiw a0, a0, 3
; RV64IMB-NEXT: addi a0, a0, 3
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: addi a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: addiw a0, a0, 10
; RV64IMB-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/and.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -195,7 +195,7 @@ define i64 @and64_0x7fffffff00000000(i64 %x) {
; RV64I-LABEL: and64_0x7fffffff00000000:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
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